Here's the final ICE update for today.... (probably)
Next up on the ICE test bench we have a Camputers Lynx (kindly loaned by Revaldhino):
This is a 4MHz Z80 based machine:
Let's replace the Z80 with the ICE-Z80:
And take a closer look:
This is a very unusual system, in that it uses BusReq/BusAck to stop the Z80 when the 6845 needs to read Video Data out of RAM, which makes it very slow indeed. It also seems to make no use of Z80 INT interrupts, and the only interrupt related instructions in the ROM Disassembly
are two DI instructions (at 0000 and 168C).
This is the first test of the ICE-Z80's BusReq/BusAck functionality, so I was expecting problems, and I was not dissapointed.
First boot did not look promising, as I was met with silence and a blank screen. Looking at memory with the ICE, I could find no evidence of ROM at address 0000 (or for that matter anywhere else) in the memory map.
Next I set a break point at 0000, power cycled the Lynx, and took another look:
Code: Select all
Ex Brkpt hit at 0000
00.000006: 0000 : DI
>> d 0
0000 : DI
0001 : LD A,$20
0003 : OUT ($80),A
0005 : JP $003B
0008 : JP $351B
000B : LD B,H
000C : LD H,C
000D : HALT
000E : LD L,C
000F : LD (HL),E
That looked better, so I started single stepping, and when the OUT instuction at 0003 was executed, the ROM promply vanished!
On the Lynx, there is a 8-bit register in the IO address space at XX7F that controls the bank switching. This is cleared by the power up reset, and for some reason this was being corrupted by the IO write to XX80.
This register turns out to be IC54, a 74LS273 which is rising edge triggered:
The clock is generated by NORing two signals:
- the output of IC63, a 74LS30 NAND gate, that is not(A6 . A5 . A4 . A3 . A2 . A1 . A0)
This part of the design is well dodgy for several reasons:
1. It doesn't use the nWR or the nRD signal, so a read of this location will corrupt the register, as will an interrupt acknowledge cycle
2. If the register is corrupted, multiple banks can be enabled for reading at the same time, causing bus conflicts (oops)
3. The write happens at the start of the IO cycle (on the falling edge or nIORQ) which is not typical
In fact, a Lynx User article
I found on the Lynx's bank switching says the following:
At this point I started to be very careful, as it's not my Lynx.
In spite of the dodgy design, it does work on a real Z80, but not on the ICE-Z80, so there is an issue here to be resolved.
To avoid damaging the Lynx, I temporarly switched to a different system, and carefully checked the ICE Z80's IO cycle timing on a scope.
The best diagrams of the Z80 bus cycles are in more recenty Z80 documentation, such as this version from 1984:
http://www.bitsavers.org/components/zil ... _Feb84.pdf
After studying these for a while, and comparing what the ICE-Z80 was outputing, there were some minor differences. These are inconsequential on most systems, but not on the Lynx.
And after fixing these (in the T80 Core), success:
(This actually takes 10 seconds to run)
So the list of Z80 systems that have been tested is now a bit longer:
- ZX Spectrum 48K (Issue 4S)
- ZX Spectrum +2B
- Acorn External Z80 Co Processor
- CPC 464
- Micro Professor MPF-1
- Camputers Lynx