I thought I would start a new thread talking about a new project I've been spending time on recently.
In the past there have been attempts to re-create the Tube ULA from scratch, given just the public specifications:
- John Kortink's ReTuLa. This is not, however a complete implementation (e.g. it doesn't support DMA used by the 80186 co-processor), and John's also not (yet...) shared the sources.
- Robert Sprow's ARM7TDMI co-proc,. Again, sadly not open source.
- BigEd and Richard Evans over at beeb816 start a Verilog project here. There was a release here, but I'm not sure how compatible it is with the original. BigEd: any comments on this? It looks pretty complete to me.
How could I possibly say no....
BigEd, and co-conspirator Chris Smith (who reverse engineered the ZX Spectrum ULA) have been in contact with Steve Furber, who worked at Acorn during the 1980s first as a hardware designer (on the BBC Micro), and later as the overall Design Manager. From Steve, they were able to ascertain that there still existed some design information from the Tube ULA, namely some of the original "check plots" produced I think by Ferranti as part of signing off the design.
Thanks to lots of hard work by Steve, we now have a very high resolution scan of one of these check plots of the Tube ULA. This is a single PNG file, weighing in at 25200 x 29388 pixels, and 1.8GB is size.
Here's a lower resolution JPG version, so you get an idea of the starting point: The core of the Ferranti ULA contains contains 9 identical blocks of 10 x 11 ULA cells. Each ULA cell contains a current source and four transistors, which is enough to make a pair of two-input NOR gates. That makes a total possible gate count of about 4000 gates.
The only part of the ULA that was customizable was the metallization layer, so in theory if you can figure out the metallization pattern, that's all you need to reverse engineer the design. What's nice is that all the routing in the core was done on an exact grid, which should help with the analysis. Each ULA cell is exactly 15 x 16 routing cells.
So, I've embarked on what I expect to be quite a long journey, towards a 100% compatible, open source Tube ULA design in Synthesisable VHDL, that could fit into the corner of a modern FPGA.
The steps that need to be completed:
1. Chop the original massive image into more manageable pieces, e.g. one image for each of the nine identical blocks of ULA cells.
2. Accurately correct the small amount of perspective distortion present in the original image. I'm not exactly sure what process Steve used to digitize the check plot, but structures that should be rectangular are very slightly parallelogram-like. It's enough to make overlaying a grid tricky. A perspective transform needs to be calculated to correct each of the array blocks.
3. Process each of these images (using GIMP or Photoshop) to quantize down to a small number of colours to make automatic extraction of the metallization pattern simpler. (e.g. make the metal and only the metal blue)
4. Superimpose the original routing grid, as accurately as possible, over the whole design. This is harder than it sounds, as even after perspective correction there are still some non-linear distortions present.
5. Look at each routing cell, and try to do some pattern matching to determine its connectivity to its immediate neighbours. Attempt to improve the results by running some design rule checking, and looking for unexpected features, like cells that look to be connected from one side, but not the other. Ideally fix these automatically, but flag the cell for manual inspection.
6. Manually identify the pin name of each peripheral cell, its configuration, and where the signals enter the core. It's easier to do this manually, as there are only 40 pins, and that saves having to write code that deals with the additional variability (and orientations) of the peripheral cells. There's plenty of documentation around that gives the Tube ULA pinout.
7. Generate a transistor level netlist for the whole design from this cell connectivity data and where the 40 (ish) external signals enter the core.
8. Process the transistor level netlist and try to reduce it down to a netlist of 2-input NOR gates.
9. Identify patterns of cross-coupled NOR gates that form latches and/or registers.
10. Eventually produce gate-level VHDL (mostly NOR gates and registers) that can be synthesised into an FPGA.
11. Test this by simulation and/or synthesis into a GODIL.
Phew! If you are still with me, then well done.
I'm currently up to about step (5).
Here's an example of what's involved....
A small portion of the original image: After correcting for the small amount of perspective distortion: After cleaning up in GIMP: After overlaying the routing grid, and performing some pattern matching to determine the layout: Some explanation of the final image is necessary:
- The fine red grid is an attempt at automatically superimposing the original routing grid.
- The green pins were placed by dead reckoning, and represent the terminals to known features in a cell (e.g. the four transistors).
- The red lines represent the connectivity information extracted by pattern matching each routing cell against a set of idealized shapes.
- The yellow squares are were design rule checks failed, and a fix was made, which needs to be manually checked.
https://www.dropbox.com/s/gig5p2nn0b667 ... 140802.png
And the analysis code (definitely a work in progress) is in GitHub.
I'm posting this now for a few of reasons:
- I don't really like doing things behind closed doors. It's feedback from other folk, and their ideas, that keep me going.
- I'm at the point where I'm convinced this is eventually going to work, i.e. the number of errors in extracted connectivity is getting close to zero.
- There are likely to be many opportunities for others to help out, such as helping to check annotated portions of the array for connection errors.