Page ROM/RAM

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banedon88
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Page ROM/RAM

Post by banedon88 » Sun May 26, 2019 10:17 pm

Hi guys

I'm trying to understand the way the beeb (model B currently) selects/utilises paged ROMs/RAM with a view to creating my own SWRAM board.
Looking at the circuit diagram I can see the following:
- IC21 is used to enable the IC20 which in turn is used to enabled the currently latched ROM. This only happens if A15=1 and A14=0 (address range &8000 to &BFFF).
- IC76 acts as a latch and is programmed via D0-D3 when /ROMSEL goes low. The output of IC76 goes to IC20 and is decoded to select the correct ROM.
- /ROMSEL only goes low (so the latch is only programmed) when the address bus = &FE30 with R/W = low (Write) via IC26.
- &F4 contains the RAM read-copy of the currently latched ROM.
- &FE30 is used for writing/changing the ROM.

What I don't understand is that the beeb lists all ROMS from 15 down to 0, with BASIC in socket 15. However, the latch is programmed using D0-D3, not D4-D7 so shouldn't the inbuilt sockets be mapped to socket 0-3?

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1024MAK
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Re: Page ROM/RAM

Post by 1024MAK » Sun May 26, 2019 10:52 pm

Have a read of this web page :wink:

To answer your last question, 4 binary bits can be decoded to 16 different control lines. This is what expansion boards do. In a model B without a sideways ROM/RAM expansion board, only partial decoding is done. Although the latch (IC76) stores 4 bits (D0 to D3 from the databus), IC20 only decodes QA and QB (bits 0 and 1) from IC76. QC and QD (bits 3 and 4) are ignored.

The end result is that there are four slots that select each sideways ROM socket on the main board. The OS however is aware of this. It scans from the highest ROM number to the lowest. But if it has already discovered a ROM, any repeats of this ROM are ignored. Hence on an unexpanded and unmodified machine the OS will normally only report ROMs in slots 15, 14, 13 and 12.

Mark
Last edited by 1024MAK on Sun May 26, 2019 10:53 pm, edited 1 time in total.

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Elminster
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Re: Page ROM/RAM

Post by Elminster » Sun May 26, 2019 11:00 pm

Was re-Reading my notes but Mark beat me to it. I was going to say only using d0-d1 as d2-d3 equate to Qc and Qd, which are just tied high (according to my notes).

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banedon88
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Re: Page ROM/RAM

Post by banedon88 » Mon May 27, 2019 10:14 am

Thanks for your responses, guys.
So does this mean that when writing the rom number to the latch your code has to convert the slot number so that it gets set properly?
I.e. :
I write &F (15) to address &FE30
The databus looks like this 00001111 (D7-0)
/ROMSEL goes low because the address bus contains &FE30. This causes IC76 to latch its inputs (from D0-3 (1111)) and output to QA to QD. We now have 1111 outputing on QA to QD.
Only QA and QB are used which are passed to inputs A & B of IC20
IC20 decodes the inputs with the following truth table (from TI 74LS139AN datasheet):
TI 74LS139AN truth table.GIF
TI 74LS139AN truth table.GIF (5.96 KiB) Viewed 1016 times
So A & B being 11 decodes to Y3 (pin 9) output going low
This causes IC101 (empty ROM scoket) to be selected - not IC52. To select IC 52 we'd have to invert the inputs to IC20 - i.e. A & B set to 0. THis can only be done by inverting the value on the databus D0-3. This is the bit that has had me confused.

Am I correct in this or have I missed something?


[edit]

I reread Michelle Knights web page (thanks for the link) and it did sort of confirm what I am thinking. Here's a truth table that I've put together:
ROMselectTruthTable.GIF
If, given that what I tihnk is true, then why is, say, 15 stored at &F4 and also written to &FE30 from what I can see from some sample rom code?
Shouldn't 15 (currently selected ROM) be written to &F4 and 00 (the value to select ROM 15) be written to &FE30 ?

[edit]
Just tested this on beebem and, as suspected, you write 15 to both locations. Does IC76 somehow invert D0-3 ? If so this would explain things.
Last edited by banedon88 on Mon May 27, 2019 11:50 am, edited 7 times in total.

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KenLowe
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Re: Page ROM/RAM

Post by KenLowe » Mon May 27, 2019 12:56 pm

I don't think your truth table is quite correct. ROM15 is IC101 and is selected by Y3 going low when D0/QA and D1/QB are both set high. So, ROM15 would be selected when the databus is 15, 11, 7 or 3 (since we're ignoring the upper 2 bits D2/QC & D3/QD).

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Re: Page ROM/RAM

Post by banedon88 » Mon May 27, 2019 1:58 pm

#-o Talk about not seeing the wood for the trees - you are quite correct with regards the repeating bit pattern.

However, with regards IC101: The BASIC ROM on the model B's that I have are all in socket IC55 (per the circuit diagram) so I naturally assumed that IC52 was rom slot 15. In fact on one of my boards IC101 doesn't even have a DIP socket on it.
Also, how does *ROMS know to not repeatedly list the same 4 ROMs on an un-expanded model B given that it's checking 0000 to 1111 and getting the same repeating 4 patterns on bits 0 & 1 with bits 2 & 3 being ignored? Does it just compare the ROM titles for duplicates?


My plan of action (given the above):
1) isolate IC20 from IC76 by removing S20 & S22 completely. This will bypass the ROM select latch.
2) have a fly lead to the middle pins of S20 & S22 so I can feed a ROM select value to IC20 from my PCB.
3) have a fly lead going to /ROMSEL so I can detect when the OS is trying to write to the ROM select latch.

The way I see it I need to bypass the ROM select latch to prevent an onboard paged ROM being selected at the same time as one form my board (i.e. bus contention).

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Re: Page ROM/RAM

Post by 1024MAK » Mon May 27, 2019 2:14 pm

Image

Note the ROM number is the same as the data bus value that is written to the ROM latch.

The inversion carried out by IC20 output lines does not matter, as the ROM chips have active low chip select (chip enable) [ /CS or /CE ] control pins.

Mark
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BBC B ROM decoding

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Re: Page ROM/RAM

Post by 1024MAK » Mon May 27, 2019 2:29 pm

banedon88 wrote:
Mon May 27, 2019 1:58 pm
However, with regards IC101: The BASIC ROM on the model B's that I have are all in socket IC55 (per the circuit diagram) so I naturally assumed that IC52 was rom slot 15. In fact on one of my boards IC101 doesn't even have a DIP socket on it.
Acorn changed their mind which socket BASIC would be fitted in. In practice, you can put it anywhere you like if it is the only language ROM in the system.
banedon88 wrote:
Mon May 27, 2019 1:58 pm
Also, how does *ROMS know to not repeatedly list the same 4 ROMs on an un-expanded model B given that it's checking 0000 to 1111 and getting the same repeating 4 patterns on bits 0 & 1 with bits 2 & 3 being ignored? Does it just compare the ROM titles for duplicates?
The basic Model B does not have a *ROMS command. Only the Master machines have this command build in.
On model B machines, there are third party ROMs that may be providing the *ROMS command.

The OS in a model B, a Master or an Electron starts at ROM 15 and reads the start of the ROM. It then makes a note of it. If it finds another ROM the same, as it is counting down through the ROM numbers 15, 14, 13, etc... down to 0, it will ignore that ROM, as it has the same details as one that it has already found.
banedon88 wrote:
Mon May 27, 2019 1:58 pm
My plan of action (given the above):
1) isolate IC20 from IC76 by removing S20 & S22 completely. This will bypass the ROM select latch.
2) have a fly lead to the middle pins of S20 & S22 so I can feed a ROM select value to IC20 from my PCB.
3) have a fly lead going to /ROMSEL so I can detect when the OS is trying to write to the ROM select latch.

The way I see it I need to bypass the ROM select latch to prevent an onboard paged ROM being selected at the same time as one form my board (i.e. bus contention).
You could just take the outputs of IC76 and feed them to your board... No need to worry about /ROMSEL then.
You can pick up QA and QB on S22 and S20, and QC and QD can be picked up off the unused holes for the not fitted diodes D4 and D5.

Mark

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sweh
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Re: Page ROM/RAM

Post by sweh » Mon May 27, 2019 2:47 pm

1024MAK wrote:
Mon May 27, 2019 2:29 pm
The OS in a model B, a Master or an Electron starts at ROM 15 and reads the start of the ROM. It then makes a note of it. If it finds another ROM the same, as it is counting down through the ROM numbers 15, 14, 13, etc... down to 0, it will ignore that ROM, as it has the same details as one that it has already found.
The results of this scan are stored in &2A1->&2B0. This will hold the ROM type (eg &82), or 0 if no ROM (or duplicate) is detected. So tools like *ROMS could use this to skip printing of the duplicates. (That's how my RAM Manager I wrote BITD worked, anyway).
Rgds
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KenLowe
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Re: Page ROM/RAM

Post by KenLowe » Mon May 27, 2019 3:34 pm

banedon88 wrote:
Mon May 27, 2019 1:58 pm
My plan of action (given the above):
1) isolate IC20 from IC76 by removing S20 & S22 completely. This will bypass the ROM select latch.
2) have a fly lead to the middle pins of S20 & S22 so I can feed a ROM select value to IC20 from my PCB.
3) have a fly lead going to /ROMSEL so I can detect when the OS is trying to write to the ROM select latch.

The way I see it I need to bypass the ROM select latch to prevent an onboard paged ROM being selected at the same time as one form my board (i.e. bus contention).
This is what I do on my Integra-B board:

ROMSel.PNG
RomSel
Sorry, it's a little bit messy. Haven't got around to tidying it up yet.

The 74LS159N is a 4/16 line decoder with open collector outputs, so it's possible to common outputs together. This is used for ROM selection.
  • Outputs 0..3 are commoned together and connect to pin 15 of IC20 (via S21sw). Together with rD0 and rD1, which connect to IC20, pins 13 & 14 (via S20c & S22c respectively), this allows the IntegraB board to use IC20 on the mainboard to select any of the 4 sockets on the mainboard (banks 0..3)
  • Outputs 4..5 are commoned together and are used to ROM select a 32k RAM bank on the IntegraB board (banks 4..5)
  • Outputs 6..7 are commoned together and are used to ROM select a 32k RAM bank on the IntegraB board (banks 6..7)
  • Outputs 8..15 are wired to 8 separate sockets (2 rows of 4) on the IntegraB board (banks 8..15). Outputs 8/9, 10/11, 12/13 & 14/15 can be commoned together via jumpers to allow the use of 32k ROM/EEPROM/RAM in the upper row. Otherwise, 8k/16k ROMS can be installed in both upper and lower rows.
Address decoding (done on a GAL) is used to latch the data (ROM number) in IC6 when the address is &FE30.
Address decoding (again done on a GAL) is used to enable the 4/16 line decoder outputs when the address is in range &8000..&BFFF (A15 & !A14)

Hope this is of some help.

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Re: Page ROM/RAM

Post by KenLowe » Mon May 27, 2019 3:41 pm

sweh wrote:
Mon May 27, 2019 2:47 pm
The results of this scan are stored in &2A1->&2B0. This will hold the ROM type (eg &82), or 0 if no ROM (or duplicate) is detected. So tools like *ROMS could use this to skip printing of the duplicates. (That's how my RAM Manager I wrote BITD worked, anyway).
Out of interest, what does the OS do to determine a duplicate and thus write 0 to the range &2A1..&2B0?

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Re: Page ROM/RAM

Post by tom_seddon » Mon May 27, 2019 4:02 pm

KenLowe wrote:
Mon May 27, 2019 3:41 pm
sweh wrote:
Mon May 27, 2019 2:47 pm
The results of this scan are stored in &2A1->&2B0. This will hold the ROM type (eg &82), or 0 if no ROM (or duplicate) is detected. So tools like *ROMS could use this to skip printing of the duplicates. (That's how my RAM Manager I wrote BITD worked, anyway).
Out of interest, what does the OS do to determine a duplicate and thus write 0 to the range &2A1..&2B0?
It compares the first 1K - see the routine at $dad1. Couldn't see where it clears the table, though...

--Tom

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Re: Page ROM/RAM

Post by banedon88 » Mon May 27, 2019 4:04 pm

They moved BASIC?? Argh. This is why I was so confused about the decoding. Cheers Acorn :mrgreen:.

To clarify: My SWR board is going to be for sideway RAM only with the ROM images being held in a single 1Mbit battery backed SRAM, with a CPLD (ATF1504AS) being used for selecting the 'banks' (i.e. A14, A15 & A16 on the SRAM) and ROMSEL decoding. I'll also be adding on a read/write switch as well to prevent images being over written).
As such, I don't want to replace the existing ROMs and so still need to do the decoding for them.

I do like the idea of controlling the enable pin (15) on IC20 - a very nice way of avoiding contention - thanks for that idea :).
I'll post a schematic in the next day or so of my progress on this.

Thanks again for all the help and information guys - very much apopreciated.
Last edited by banedon88 on Mon May 27, 2019 4:07 pm, edited 1 time in total.

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Re: Page ROM/RAM

Post by jgharston » Mon May 27, 2019 8:47 pm

tom_seddon wrote:
Mon May 27, 2019 4:02 pm
KenLowe wrote:
Mon May 27, 2019 3:41 pm
sweh wrote:
Mon May 27, 2019 2:47 pm
The results of this scan are stored in &2A1->&2B0. This will hold the ROM type (eg &82), or 0 if no ROM (or duplicate) is detected. So tools like *ROMS could use this to skip printing of the duplicates. (That's how my RAM Manager I wrote BITD worked, anyway).
Out of interest, what does the OS do to determine a duplicate and thus write 0 to the range &2A1..&2B0?
It compares the first 1K - see the routine at $dad1. Couldn't see where it clears the table, though...
The ROM table is cleared as part of setting up page 2; after copying the default vectors and OSBYTEs, at LDA42 it clears the rest up to &2CD then sets the rest up to &2FF to &FF to set all the buffers to 'empty'.

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

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banedon88
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Re: Page ROM/RAM

Post by banedon88 » Sat Jun 01, 2019 6:32 pm

Here's my latest design. Got the PCB designed, as well as the CPLD code.
If anyone spots any problems then please let me know - gonna send this off soon to be fabricated and would rather know of anything I've missed before hand :).

Overview:
BeebSWR is an 8 x 16KB bank paged RAM board designed to work along side the existing phycial ROM sockets on the BBC Micro model B. It has a battery backup solution and ability to prevent writing to its own RAM banks.

Fitting:
The PCB is fits into the 6502A CPU socket with a socket on it for the processor itself. All pins from the CPU are routed to the mainboard.
- S21(sw-se / bottom-most) jumper on the mainboard should be delinked/removed and the "S21sw" pin on BeebSWR connected to the now-exposed sw pins (left hand one) on the mainboard. Please note that the S21ne-nw / top-most jumper should be left where it is.
- "/ROMsel" pin the on BeebSWR should be connected to either IC26 pin 5 or IC76 pin 9 on the mainboard.
- Only connect "Aux Pwr" pin header to the main red/black +5/0v power lines from the mainboard psu if required. This connection is included as a precaution only.
- A switch can be connected to the "Write Prot." pin header on BeebSWR. This can be used to enable or disable writing to the BeebSWR RAM banks. If not fitted then writing is allowed.

How it works:
BeebSWR has a latch (IC3) which keeps track of which ROM bank is currently selected. It does this by detecting when /ROMSEL goes low - which happens when address &FE30 (the address of the ROM select latch) is written to. When /ROMSEL goes low, IC3 latches D0-3 from the BBC Micros databus as this is the ROM number being selected.
The BBC Micro does exactly the same thing using IC76. IC76 feeds the latched / selected ROM bank to IC20 (a 2 to 4 line decoder) which is used to select the appropriate physical ROM socket.
BeebSWR subverts this process by controlling IC20 via IC4 on BeebSWR. If it believes that one of its paged RAM banks should be selected then it disables IC20 completely via it's enable pin which means no physical ROM socket will be enabled. This decision is determined by which RAM bank is being selected:

ROM banks 15-12 - BBC Micro physical ROM sockets used. IC20 enabled (pin 15 = 1).
ROM banks 11-4 - BeebSWR 16KB RAM banks used. IC20 disabled (pin 15 = 0).
ROM banks 3-0 - Neither is used - future expansion possibility.

The battery is a CR2032 coin type one which is utilised by a DS1218 (IC6) to supply power and also filter the /CE (chip enable) pin of BeebSWR's RAM (IC5). If the main power dips low then the battery is switched in and /CE is prevented from going low / being enabled. This prevents spurious/random writes to the RAM as the BBC Micro loses power or when it powers up.
BeebSWR_v1.0_ModelB.gif
Last edited by banedon88 on Sat Jun 01, 2019 6:35 pm, edited 1 time in total.

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Re: Page ROM/RAM

Post by IanS » Sat Jun 01, 2019 7:52 pm

Suprised you can't put the latch (74ls75) in the CPLD.

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Re: Page ROM/RAM

Post by banedon88 » Sat Jun 01, 2019 8:24 pm

I'll admit to not being wiz using WinCUPL/ABEL and so my last effort at making one didn't work out well. I'll give it another go as saving an IC would be useful.

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Re: Page ROM/RAM

Post by banedon88 » Sat Jun 01, 2019 9:43 pm

OK this is what I've got :

Code: Select all

/* inputs */

Pin [18..21] =  [D0..3];
Pin 5  =  E;        /* latches D0-3 when high */

/* Qx (and nQx) are virtual pins as we don't need to output - just use the results. */

Q0 = !(nQ0 # (!D0 & E));
nQ0 = !(Q0 # (D0 & E)); 

Q1 = !(nQ1 # (!D1 & E));
nQ1 = !(Q1 # (D1 & E)); 

Q2 = !(nQ2 # (!D2 & E));
nQ2 = !(Q2 # (D2 & E)); 

Q3 = !(nQ3 # (!D3 & E));
nQ3 = !(Q3 # (D3 & E)); 

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Re: Page ROM/RAM

Post by IanS » Sat Jun 01, 2019 10:09 pm

You seem to simulating a latch, doesn't the chip have them built in?

The 22V10 I use for IDE podules has a dedicated Clock pin, so I just define the latched signals as Q0.D = D0. I assume you'd have to define the clock using .CK. e.g. C0.CK = E (untested).

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Re: Page ROM/RAM

Post by banedon88 » Sat Jun 01, 2019 11:02 pm

I think it can - I'm just having issues figuring out how. I'll keep at it, but worse case I'll use the method previously stated.

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Re: Page ROM/RAM

Post by banedon88 » Sat Jul 13, 2019 9:03 pm

Evening all.

Here's an update of this project. Things were slowed down by a number of issues (see below) and also needing to get my hands on a Smart SPI SD card adapter/rom from RetroClinic to save images and test programs (typing them each time the machine was reset got old very, very quickly!). This wasn't due to retroclinic - just me not having the funds until recently.

Images:
1.PCBTopSide.jpg
2.PCBUnderside.jpg




Bug list:

Issue: Writing to Sideways RAM not qualified with the BBC Micro clock
Status: Resolved
Details: I realised this silly design mistake just after I ordered the PCBs (30 of them...). Ran a bodge wire from PH1O (pin 3) on the 6502A socket to a free pin on the CPLD and modified the CPLD firmware. Writing to the Sideway RAM IC on BeebSWR now occurs on PH1O being high. This ensures the address and data buses on the BBC Micro have had time to settle their values.

Issue: The turned pins of the BeebSWR interface damages the old style 40pin DIP socket used on the BBC Micro CPU socket
Status: Short term, but long term required
Details: I've replaced the 40pin DIP socket on the BBC Micro main board with a modern turned pin style one. However, this is not a suitable solution. I'll see if I can find a turned pin to old 'wipe' style adapter. Might have to make one....

Issue: No language ROM detected on BBC MIcro boot
Status: Resolved
Details: Caused by a firmware issue in the CPLD. I had qualified Paged ROM access by A14 & A15, but got them the wrong way around. Firmware updated.

Issue: Corrupted data written to Sideway RAM on BeebSWR
Status: Resolved
Details: Intermittent connection issue with D2 on the Sideway RAM IC. Reflowed and now is reliable and no corruption occurs

Issue: Contents of the Sideway RAM on BeebSWR currupts on BBC Micro reset
Status: Resolved
Details: I've qualified the Chip Enable pin of the Sideways RAM IC with the reset signal from the 6502A. A bodge wire was added between the 6502A's RESB (reset, pin 40) and a free pin on the CPLD. The CPLD firmware was also modified.

Issue: Test ROM images appear to duplicate upon BBC Micro reset
Status: Not resolved
Details: I'm still looking into this. I'm trying to determine if the test image is being duplicated when written, or there's another reason. So far I can see that the image writes correctly with the expected result ina *ROMS output. However, upon restarting the BBC Micro, *ROMS will show the test image in the next RAM bank up. So if an image was written to bank 8 then it'd show up as bank 8 until a reset. Then it would appear in bank 9.

Loading the test image and the initial *ROMs result. All looks good with test image in bank 8:
3.LoadTestImg.jpg
Soft (BREAK key) reset and next *ROMs result. Test image now appears in bank 9:
4.AfterSoftReset.jpg
Power cyle (off, wait 5 seconds, then back on) and final *ROMs result. Test image still appears in bank 9:
5.AfterPowerCycle.jpg

So, the project is actually getting there and I'm enjoying the heck out of designing, coding and creating it. Just got to work out the above kinks and it's good to go :mrgreen: . I could then perhaps sell a few (at cost) on ebay, but I'll be sure to test the design to death before then. Might even create an optional Paged ROM with some handy utilities for ROM image handling.

BTW if anyone has any constructive comments about how I've implemented this then fire away - life is a learning process after all!
Last edited by banedon88 on Sat Jul 13, 2019 9:08 pm, edited 1 time in total.

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Re: Page ROM/RAM

Post by cmorley » Sat Jul 13, 2019 9:51 pm

banedon88 wrote:
Sat Jul 13, 2019 9:03 pm
I could then perhaps sell a few (at cost) on ebay, but I'll be sure to test the design to death before then. Might even create an optional Paged ROM with some handy utilities for ROM image handling.

BTW if anyone has any constructive comments about how I've implemented this then fire away - life is a learning process after all!
Glad to hear your having fun. That is the point of it all :D

Get some of the thinner turned pin headers. The pin diameter is close to the thickness of an IC leg so will fit better.

Selling at cost on eBay is a bad idea IMO. All it takes is one problem & you'll be out of pocket. Work out a sensible markup which covers fees, postage and packaging, (some/all of) your dev costs, BOM costs, the cost of a lost board and a some money to take into the next project. Selling can be stressful and can taint what should be fun. One of our mods found this out the hard way :(

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Re: Page ROM/RAM

Post by KenLowe » Sat Jul 13, 2019 9:56 pm

Looks like you're making good progress.

For info, my IntegraB board generates /WDS and /RDS signals, and these feed into the /WE and /OE inputs of my RAM (62256 in my case):
nRDS.PNG
RAM.PNG
Where PHI1 comes from 6502 pin 3, and RnW comes from 6502 pin 34.

The rb4_5 & rb6_7 signals come from a 4 / 16 line decoder. The 4 bit inputs come from a latch, which latches data bits d0..d3 when the address is &FE30. The 4 / 16 line decoder is enable signal (/G1) is driven low when address is &FE30 and Phi1 is low.
cmorley wrote:
Sat Jul 13, 2019 9:51 pm
Selling at cost on eBay is a bad idea IMO. All it takes is one problem & you'll be out of pocket. Work out a sensible markup which covers fees, postage and packaging, (some/all of) your dev costs, BOM costs, the cost of a lost board and a some money to take into the next project. Selling can be stressful and can taint what should be fun. One of our mods found this out the hard way :(
...and I completely agree with those sentiments.

Edit: The Advanced ROM Manager is also a useful ROM to help with diagnosing SWRAM issues. The *REX function allows to view the contents of a given SWRAM, and Ctrl-R will jump to the same address at the next SWRAM, so you can see if it's duplicated or not. Obviously you need to be able to reliably run the ROM in the first instance!
Last edited by KenLowe on Sat Jul 13, 2019 10:08 pm, edited 2 times in total.

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Re: Page ROM/RAM

Post by banedon88 » Sun Jul 14, 2019 10:36 am

Hi guys

Thanks for the feed back and advice :).

I'll take onboard what you both say about selling on ebay. I'm not entirely sure the project will be worth me selling given that the components could be costly (the DS1812+ IC is £7+ al by itself). However, there are many optional extras such as the entire battery backup section (which includes the DS1812+), the LED/resistor combo, and a few other bits. This could bring the price down a fair way so could offer 1) bare PCB, 2) PCB+all parts kit, 3) PCB+ bare minimum parts. Something to think on.

@KenLow I like the functional but minimal /WDS and /RDS solution - something I will keep in mind in the future. For now it's all being sorted by the CPLD (lots of free spare pins). Also, good call on the Advanced ROM Manager (ARM) as I've never used it before. As you say, the *REX command makes life so much easier. I did find one issue with it though: When I was testing it within Beebem it had a habit of overwriting rom copyright string in sideways RAM after a restart. So (C) becomes (9). I removed the ARM rom and found that this no longer happens. ROM copy protection?

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KenLowe
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Re: Page ROM/RAM

Post by KenLowe » Sun Jul 14, 2019 10:51 am

banedon88 wrote:
Sun Jul 14, 2019 10:36 am
Also, good call on the Advanced ROM Manager (ARM) as I've never used it before. As you say, the *REX command makes life so much easier. I did find one issue with it though: When I was testing it within Beebem it had a habit of overwriting rom copyright string in sideways RAM after a restart. So (C) becomes (9). I removed the ARM rom and found that this no longer happens. ROM copy protection?
I've never seen that happen before. I seem to recall that there's a couple of different versions around. I'm using version 1.13 in case that makes any difference.
Edit: And I run it without any issue in SWRAM without any write protection.
Last edited by KenLowe on Sun Jul 14, 2019 11:06 am, edited 1 time in total.

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Re: Page ROM/RAM

Post by banedon88 » Sun Jul 14, 2019 12:02 pm

I'm running the same version. I'll go through and see if I can spot the code responsible.

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Re: Page ROM/RAM

Post by banedon88 » Sun Jul 14, 2019 8:06 pm

Well, I can't seem to replicate the issue with the rom image being swapped into another rom slot on reset. I.e. If you load an image into slot 8, will list as slot 8, but if BREAK is pressed then it comes up after that in slot 9 (and reading 8 would return it as well).
Now it stays in the correct slot. Maybe bad connection, but I dislike not knowing why it disappeared :? . Will keep testing.

BTW is anyone here a whiz on WinCUPL? I know how to use it within reason, but I am really struggling with trying to implement a D-latch in an ATF1504AS CPLD. Just cannot get it to work and I was hoping to drop the 4 bit external latch out of my design (reduced costs & gain back the PCB real estate involved).
Any ideas? It's driving me nuts - I think I've now give myself concussion from head-butting my desk in frustration :wink: :mrgreen:
Last edited by banedon88 on Sun Jul 14, 2019 8:07 pm, edited 1 time in total.

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Re: Page ROM/RAM

Post by KenLowe » Sun Jul 14, 2019 10:38 pm

Have you had a look at the reference guide?

http://ee-classes.usc.edu/ee459/library ... erence.pdf

Most of my experience is with the GAL22V10 & GAL16V8. With these devices, pin 1 is defined as the clock pin when the pld is being used in 'registered' mode. I'm guessing the PLD that you're using will be similar.

Here's a GAL16V8 example that I've used in the past:

Code: Select all

/* ***********************************************/
/* PALPROM design for Inter-Word                 */
/* ***********************************************/
/* Bank 0 switching address 1: 0x804x            */
/* Bank 0 switching address 2: 0xBFAx            */
/* Bank 1 switching address 1: 0x806x            */
/* Bank 1 switching address 2: 0xBFCx            */
/* Bank 1 switching address 3: 0xBFEx            */
/* ***********************************************/

Name     CC2 PALPROM ;
PartNo   00          ;
Date     14/02/2019  ;
Revision 01          ;
Designer Ken Lowe    ;
Company  NA          ;
Assembly None        ;
Location             ;
Device   G16V8       ;


/* *************** INPUT PINS *********************/

PIN 1     = CLK;
PIN 2     = A12;
PIN 3     = A7;
PIN 4     = A6;
PIN 5     = A8;
PIN 6     = A9;
PIN 7     = A5;
PIN 8     = A11;
PIN 9     = A10;
PIN 11    = GND;     /* Set to GND for registered operation */

PIN 12    = nCE;
PIN 13    = nOE;
PIN 18    = A13;


/* *************** OUTPUT PINS *********************/

PIN 15    = !A14RESET; /* Intermediate feedback latch, not connected on PCB */
PIN 17    = !A14OUT;   /* A14 to 27C256 */
PIN 19    = !ENBOUT;   /* To Clk PIN 1 on GAL */


/* *************** EQUATIONS ***********************/

0x804x     = !A13 & !A12 & !A11 & !A10 & !A9 & !A8 & !A7 &  A6 & !A5;
0x806x     = !A13 & !A12 & !A11 & !A10 & !A9 & !A8 & !A7 &  A6 &  A5;
0xBFAx     =  A13 &  A12 &  A11 &  A10 &  A9 &  A8 &  A7 & !A6 &  A5;
0xBFCx     =  A13 &  A12 &  A11 &  A10 &  A9 &  A8 &  A7 &  A6 & !A5;
0xBFEx     =  A13 &  A12 &  A11 &  A10 &  A9 &  A8 &  A7 &  A6 &  A5;

BANK0      = 0x804x # 0xBFAx;
BANK1      = 0x806x # 0xBFCx # 0xBFEx;
A14RST     = BANK0;


/* *************** COMBINATORIAL OUTPUTS ***********/

ENBOUT     = !nCE & !nOE;


/* *************** REGISTERED OUTPUTS **************/

A14RESET.d = BANK0;
A14OUT.d   = BANK1 # (A14OUT & !A14RST);
Last edited by KenLowe on Sun Jul 14, 2019 10:39 pm, edited 1 time in total.

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banedon88
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Re: Page ROM/RAM

Post by banedon88 » Tue Jul 16, 2019 5:08 pm

Hi KenLow

Thanks very much indeed.

I'll give this a go in a 22V10 PAL first and then CPLD. I'm waiting for my new EEPROM programmer to arrive (Batronix BX48 Batego II), so in the mean time will see if WinCUPL will behave long enough for me to try and simulate something :D.

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