MEMC nibble mode ROM access / ROM emulation

Arc/RPCs, peripherals, RISCOS operating system & ARM kit eg GP2x, BeagleBoard
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myelin
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MEMC nibble mode ROM access / ROM emulation

Post by myelin » Wed Nov 07, 2018 8:28 pm

It looks like MEMC has a single-cycle ROM access mode for sequential accesses, "200ns with 60ns nibble-mode", configured by setting bits 7:6 (for high ROM) or 5:4 (for low ROM) of the MEMC Control Register to '11'. This is documented in section 6.5 of the MEMC datasheet (0460,019, 1986). This has been replaced by "Not Meaningful", however, in the definition in the VL86C110 (MEMC1A) datasheet (Fig 6, page 4-13, VTI ARM databook 1990).

I'm puzzling over making a ROM emulator so I can try out boot code in my A3000 without having to remove chips for reprogramming, and wondering if this fast nibble-mode was ever used, or if it's safe to assume that I'll always have 200ns to handle a read. Did the MEMC1A remove support for nibble-mode access, or was it just never officially used? From this thread from 2015, it looks like some programs called SYS "OS_UpdateMEMC", 64, 64 to turn it on when running at 8MHz, but this broke under RISC OS 3.

Does anyone have an A3000 with MEMC1A running RISC OS 2? If so, could you try running SYS "OS_UpdateMEMC", 64, 64, and see if it gives you a speed boost or a crash?
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davidb
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Re: MEMC nibble mode ROM access / ROM emulation

Post by davidb » Thu Nov 08, 2018 12:29 am

Anecdotal evidence: our A3000 would always hang when SYS "OS_UpdateMEMC", 64, 64 was used. I don't remember if this was under RISC OS 2 or 3.

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Re: MEMC nibble mode ROM access / ROM emulation

Post by steve3000 » Thu Nov 08, 2018 12:39 am

It works fine on RISC OS 2 and MEMC1A, I still use it occasionally on my A3000. :)

The problem was with RISC OS 3, not MEMC1A. The ROM chips that RISC OS 3 was supplied on typically could not operate at the faster speed, so the machine crashed when old RO2 developed BASIC programmes called this under RO3, to increase their speed.

As I recall the ROM access speed on startup is always the slowest - 450ns.

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myelin
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Re: MEMC nibble mode ROM access / ROM emulation

Post by myelin » Thu Nov 08, 2018 1:50 am

Excellent... I think I can make this work.

I'm trying to do it with a single 16-bit wide flash chip, and do two accesses per host access. Luckily the flash chip I'm looking at (S29GL064N) has a compatible page mode; the first access takes 90ns and subsequent accesses within a 16-byte page take 25ns. That means 115ns for the first 32 bits and 50ns for subsequent 32-bit accesses within the page, which should fit comfortably within the timing window.

This also suggests an easier project: burning RISC OS 3 into some 70ns flash chips, which should work with the faster memory timings.
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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SarahWalker
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Re: MEMC nibble mode ROM access / ROM emulation

Post by SarahWalker » Thu Nov 08, 2018 6:19 pm

steve3000 wrote:
Thu Nov 08, 2018 12:39 am
As I recall the ROM access speed on startup is always the slowest - 450ns.
On MEMC reset, yes. RISC OS will measure memory speed during POST and choose a more appropriate setting; on an 8 MHz machine it will select 200ns.
Last edited by SarahWalker on Thu Nov 08, 2018 6:20 pm, edited 1 time in total.

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