My first (large) CPLD steps (XC9572)

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bprosman
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My first (large) CPLD steps (XC9572)

Post by bprosman » Sun Sep 16, 2018 9:03 am

Good morning,

To replace "glue logic" in my CPU boards (to be designed) im working with XC9572 and the EPM3064.
Even though I know they are obsolete ,the TQFP packages are still widely avaialable.
With the EPM3064 I made a memory decoder but that was all done by "schematic entry" now my first steps in the VHDL area and to be honest not a successfull one. So hoping from some help from the experts here (Dave "Hoglet" ?).

I have made some adapter boards to work with them and test.
First of all what confuses me is the power supply. I know Roland (Leurs) has used them on his Atom designs and always was under the impression that they were 3V3 supply voltage and 5V "tolearant" , thats also what the Datasheet says.
DS057 says 3V3
DS057-XC9572.pdf
(199.05 KiB) Downloaded 3 times
DS065 says 5V
DS065-XC9572.pdf
(120.55 KiB) Downloaded 3 times
But... I've found a second datasheet that mentions 5V and also a Xilinx evalulation board with the XC9535 powers it with 5V.
Also a Xilinx appnote (with the XC9536) seems to power it with 5V.
DS057-XC9572.pdf
(199.05 KiB) Downloaded 3 times
So far the first part of the problem :-)
I kinda rebuilt XAPP078 with my TQFP-100 part
IMG_7297.jpg
IMG_7304.JPG
And trying some VHDL examples.
First I tried the VHDL example provided in XAPP078 that one didnt "Compile" as it stumbled over the "Metamor" declarations and didnt reconize "Dout". Pins I used :55,56,58,64,67,68,70,74

Code: Select all

library IEEE;
use IEEE.std_logic_1164.all;
library metamor;
use metamor.attributes.all;
entity jcounter is
port (
clk:in STD_LOGIC;
Dout:buffer STD_LOGIC_VECTOR (7 downto 0)
);
-- Can use attributes to assign pin locations in Foundation VHDL
attribute pinnum of Dout:signal is "p13,14,16,18,19,20,21,22";
end jcounter;
architecture jcounter_arch of jcounter is
begin
process (CLK)
begin
if CLK'event and CLK='1' then--CLK rising edge
Dout(7 downto 1) <= Dout(6 downto 0);--Shift register
Dout(0) <= not Dout(7);--Last bit inverted back into first bit
end if;
end process;
end jcounter_arch;
Then I tried this one but the code is not really completely visible :
https://www.youtube.com/watch?v=SJIarQQEYmY

So hoping for someone who can give me a jumpstart.
Further struggling getting the programmer to work on W10 but that is another issue.

Thanks all in advance,
Bram
Attachments
xapp078.pdf
(33.07 KiB) Downloaded 2 times

dominicbeesley
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Re: My first (large) CPLD steps (XC9572)

Post by dominicbeesley » Sun Sep 16, 2018 9:33 am

If you have the correct ones and not knock off rebadged onea then you should be able to tie all the vccio and vccint to 5v. You may be (read probably will) be getting problems due to not having adequate decoupling close enough to the chip. I cant see if your board has decoupling caps but ive found that to avoix problems that each supply line needs decoupling to a good solid ground as close to the chip as is possible. A few inches of trace pins and then breadboard can make them a but lively and prone to glitches and lockups

Edit: the tied supplies is for the xc95 chips i cant remember for the epm chips
Last edited by dominicbeesley on Sun Sep 16, 2018 9:36 am, edited 1 time in total.

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danielj
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Re: My first (large) CPLD steps (XC9572)

Post by danielj » Sun Sep 16, 2018 10:16 am

That's a 9572XL - they are 3.3V supply - 5V may well make them quite grumpy. The 9572 non-XL parts are OK with a 5V supply IIRC. The inputs will on all, however, tolerate 5V.

Common arrangement is to rig up a LM1117MP-3.3 voltage regulator with 2x10uF tants - 1 on the 5V in and one on the 3.3V out.

d.
Last edited by danielj on Sun Sep 16, 2018 10:16 am, edited 1 time in total.

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hoglet
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Re: My first (large) CPLD steps (XC9572)

Post by hoglet » Sun Sep 16, 2018 10:20 am

Bram,

Firstly on supply voltage - the XC9572 and XC9572XL are different parts
- XC9572 - needs a 5V supply
- XC9572XL - needs a 3.3V supply (I/Os are 5V tolerant)

The part on your boards seems to be a XC9572XL, so VCC must be fed with 3.3V.

Second, as Dominic says, it is important to get some decoupling capacitors between VCC and GND close to the chip.

Third, I don't know what this library is:

Code: Select all

library metamor;
use metamor.attributes.all;
But it's non standard so best to just use the standard libraries if possible.

Fourth, it's more standard to define pinouts in a separate .ucf file. Here's an example:
https://github.com/hoglet67/RGBtoHDMI/b ... toHDMI.ucf
That should be added to the project in ISE.

Finally, what are you using as a clock? If it's a switch, it will need debouncing or you will see multiple transitions. Maybe as a starting point, just try to set the LEDs to fixed values, some on and some off. That will let you check the connectivity and programming.

Dave

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Re: My first (large) CPLD steps (XC9572)

Post by bprosman » Sun Sep 16, 2018 11:33 am

Thanks for the quick responses.
- XC9572 - needs a 5V supply
- XC9572XL - needs a 3.3V supply (I/Os are 5V tolerant)
Ok so that is clear. With regards to the decoupling caps, I put some on, though I tied the VccLogic's together as well as the VccIO's . And put a cap on both. Hope that is sufficient.
XC9572 Bottom.JPG
As a clock I will use a crystal oscillator in the 10MHz to 50MHz range, not sure what I have in the junkbox.
Let me first (re)install ISE Web (as that didnt start anymore under W10) as well as the programmer and come back.

Kind regards, Bram

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Re: My first (large) CPLD steps (XC9572)

Post by dominicbeesley » Tue Sep 18, 2018 10:17 am

That should be ok but not for an XL part... they do run on 3.3V but are 5V tolerant so your chip may well be goosed. The _real_ XC9572 without the XL should be cool on 5V though.

In terms of board layout I add a 100nf capactor for each supply pin and have a ground plane, long ground traces often lead to "ground bounce" so the chip will see a nice solid 5V supply but from its point of view the rest of the world is bouncing up and down this can quickly lead to noise/glitches.

There's a number cheap lctech XC9572XL boards on ebay, it might be worth making your prototype with one of those and then reverse engineering the circuit. For around a tenner they come with a regulator and 50MHz crystal...but not much info!

5Vishnes is becoming a difficulty I have now given up and started doing most stuff in 3.3V or even 1.8V where I must. on the plus side the TI level shifter chips such as the SN74CB3T16211 give more or less "free" level shifting. Just connect the 3V stuff to one side and the 5V stuff to the other side and it "just works".

D
Last edited by dominicbeesley on Tue Sep 18, 2018 10:17 am, edited 1 time in total.

Prime
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Re: My first (large) CPLD steps (XC9572)

Post by Prime » Tue Sep 18, 2018 2:34 pm

Just to clarify one point about voltakes that tripped me up.

VCCIO can be run at or BELOW the vcccore voltage so for a XC9572XL chip they'll need to run at 3.3V, input levels are however 5V tollerent. Output levels will however only be up to VCCIO, this hasn't generally been a problem in any of the Acorn / Dragon related projects that I have used them in.

Cheers.

Phill.

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danielj
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Re: My first (large) CPLD steps (XC9572)

Post by danielj » Tue Sep 18, 2018 3:45 pm

It's fine interfacing with ttl, I think it barfs with cmos (which is why the internal vfs adaptor for the beebscsi needed a buffer to sort the levels out).

d.

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Re: My first (large) CPLD steps (XC9572)

Post by bprosman » Thu Sep 27, 2018 10:01 am

It's alive :-)
I know can start using this adapter print in my CPU (19") projects.
Same for the EPM3064 on its way.
IMG_7342.JPG
https://youtu.be/wHxNcpQ61sU

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JudgeBeeb
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Re: My first (large) CPLD steps (XC9572)

Post by JudgeBeeb » Thu Sep 27, 2018 11:49 pm

You appear to be pretty much at the stage I am was wit VHDL a few weeks ago.

First of all, have a look at this book: https://github.com/hamsternz/IntroToSpa ... GABook.pdf. It is probably the best VHDL tutorial out there. I certainly found it invaluable.

Secondly, my first attempt at XISE was, like you, by way of schematic capture. XISE will provide a complete VHDL listing that is functionally equivalent to the schematic. What I did, was to take that generated VHDL as a known working starting point and then to make changes to that. That way, it was easier to spot the bugs when it didn't work as expected.

Finally, it has been suggested to me that Verilog is much easier to learn and that I should have a look at that.

In terms of hardware, I started off with this: https://www.ebay.co.uk/itm/192443477413. Fuller details and schematic are here: https://www.openimpulse.com/blog/produc ... ent-board/.
Last edited by JudgeBeeb on Thu Sep 27, 2018 11:50 pm, edited 1 time in total.
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BigEd
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Re: My first (large) CPLD steps (XC9572)

Post by BigEd » Fri Sep 28, 2018 7:47 am

(I'd be tempted to say that Verilog is the lower level language: it is C to VHDL's Pascal. As such, Verilog is harder to master, but less verbose and you'll be more productive for small projects. For huge projects, where type-safety might save a lot of anguish, maybe VHDL would win. Certainly I'd expect a first cut of something which works to be easier in Verilog. Where Verilog falls down is tutorials: I haven't yet found a great one, so I end up copy-pasting rather than understanding the language. But then, C is also notoriously difficult to understand properly, and yet not too difficult to be able to write a hundred lines of C.)

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Re: My first (large) CPLD steps (XC9572)

Post by Prime » Fri Sep 28, 2018 8:16 am

When I first started doing programmable logic stuff with CPLDs, I looked at both Verilog and VHDL and came to the conclusion that Verilog was the one that suited me the best. It was less verbose and I loked the syntax a little better than VHDL.

Whichever you use one thing that needs to be stated is that though the code looks like a procedural program where things happen one after another, it isn't you are describing hardware, where generally unless something is clocked everything happens continuously, so you may have several blocks of HDL code but change an input and the output will reflect this straight away.

What I really like about HDLs is you can do stuff like :

Code: Select all

if ((Addr[15:0] >= 16'h8000) && (Addr[15:0] < 16'hC000))
  nROM = 1'b0;
else
  nROM = 1'b1;
endif
And it will sort out the gates it needs to implement this, and will know for example that this only needs to depend on the top 4 address bits so will only use them. And yes I know there are more consise ways of expressing this :) :)

If you looks at the equations that webpack produces when you have compiled your code you can see the logic it produces, I sometimes do this as a 'logical check' to see my code produces the expected logic.

Cheers.

Phill.

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Re: My first (large) CPLD steps (XC9572)

Post by bprosman » Sun Sep 30, 2018 7:50 am

Thanks for your replies, I mainly will use this for memory decoders and small glue logic like the example Prime mentioned.

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Re: My first (large) CPLD steps (XC9572)

Post by jonb » Sun Sep 30, 2018 12:06 pm

danielj wrote:
Sun Sep 16, 2018 10:16 am
That's a 9572XL - they are 3.3V supply - 5V may well make them quite grumpy. The 9572 non-XL parts are OK with a 5V supply IIRC. The inputs will on all, however, tolerate 5V.

Common arrangement is to rig up a LM1117MP-3.3 voltage regulator with 2x10uF tants - 1 on the 5V in and one on the 3.3V out.

d.
So, a circuit that enables both parts to be fitted (with selection) might look like this?
5v-3.3v-CPLD power selector.JPG
Set J6 to select the right voltage for the 9536 CPLD

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danielj
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Re: My first (large) CPLD steps (XC9572)

Post by danielj » Sun Sep 30, 2018 12:16 pm

Yes, I think so - here's the one from the FreeFi232 which also needed 3.3V:
vreg.png

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Re: My first (large) CPLD steps (XC9572)

Post by dominicbeesley » Sun Sep 30, 2018 8:43 pm

With a few more caps close to the chip and after any jumper which could be inductive enought to introduce problems

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Re: My first (large) CPLD steps (XC9572)

Post by Prime » Sun Sep 30, 2018 9:22 pm

dominicbeesley wrote:
Sun Sep 30, 2018 8:43 pm
With a few more caps close to the chip and after any jumper which could be inductive enought to introduce problems
I think the general rule is one 0.1uf for every pair of voltage / ground pins. So for the 44 pin Xilinx I normally use 3, more for the 100 pin variants. Actually often use the 2.5mm pth ones, as I can use them to link the power through the board.

Cheers.

Phill.

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