To replace "glue logic" in my CPU boards (to be designed) im working with XC9572 and the EPM3064.
Even though I know they are obsolete ,the TQFP packages are still widely avaialable.
With the EPM3064 I made a memory decoder but that was all done by "schematic entry" now my first steps in the VHDL area and to be honest not a successfull one. So hoping from some help from the experts here (Dave "Hoglet" ?).
I have made some adapter boards to work with them and test.
First of all what confuses me is the power supply. I know Roland (Leurs) has used them on his Atom designs and always was under the impression that they were 3V3 supply voltage and 5V "tolearant" , thats also what the Datasheet says.
DS057 says 3V3 DS065 says 5V But... I've found a second datasheet that mentions 5V and also a Xilinx evalulation board with the XC9535 powers it with 5V.
Also a Xilinx appnote (with the XC9536) seems to power it with 5V. So far the first part of the problem
I kinda rebuilt XAPP078 with my TQFP-100 part And trying some VHDL examples.
First I tried the VHDL example provided in XAPP078 that one didnt "Compile" as it stumbled over the "Metamor" declarations and didnt reconize "Dout". Pins I used :55,56,58,64,67,68,70,74
Code: Select all
library IEEE; use IEEE.std_logic_1164.all; library metamor; use metamor.attributes.all; entity jcounter is port ( clk:in STD_LOGIC; Dout:buffer STD_LOGIC_VECTOR (7 downto 0) ); -- Can use attributes to assign pin locations in Foundation VHDL attribute pinnum of Dout:signal is "p13,14,16,18,19,20,21,22"; end jcounter; architecture jcounter_arch of jcounter is begin process (CLK) begin if CLK'event and CLK='1' then--CLK rising edge Dout(7 downto 1) <= Dout(6 downto 0);--Shift register Dout(0) <= not Dout(7);--Last bit inverted back into first bit end if; end process; end jcounter_arch;
So hoping for someone who can give me a jumpstart.
Further struggling getting the programmer to work on W10 but that is another issue.
Thanks all in advance,