Open Source Logic Analyzer Experiments

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Fri May 17, 2019 1:02 pm

I dont use windows, but usually when you install cygwin it installs various redhat linux libraries so you can compile c stuff.

Not sure you would get that using a built in bash prompt.

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danielj
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Re: Open Source Logic Analyzer Experiments

Post by danielj » Fri May 17, 2019 1:21 pm

You do. Windows Linux subsystem. Ubuntu or debian. Bit finnecky with some x-stuff but absolutely fine for building at the command line.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Fri May 17, 2019 1:33 pm

danielj wrote:
Fri May 17, 2019 1:21 pm
You do. Windows Linux subsystem. Ubuntu or debian. Bit finnecky with some x-stuff but absolutely fine for building at the command line.
Witchcraft.

I am near tempted to start a windows VM and try that myself .....

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Fri May 17, 2019 1:59 pm

vanekp wrote:
Fri May 17, 2019 12:58 pm
What am I doing Wrong ?
There is a script called build.sh that contains the commands that I use to build it.

Try running that script, i.e.:

Code: Select all

bash build.sh
This is what the script currently contains:

Code: Select all

#!/bin/bash

LIBS="-lm"

if [[ $OS = *"Windows"* ]]; then
  LIBS="$LIBS -largp"
fi

gcc -Wall -O3 -D_GNU_SOURCE -o decode6502 src/main.c src/em_6502.c src/profiler.c src/profiler_instr.c src/profiler_block.c src/profiler_call.c src/tube_decode.c $LIBS
(In Windows 10, I'm not sure if you will need the additional -largp library or not.)
Last edited by hoglet on Fri May 17, 2019 2:29 pm, edited 2 times in total.

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vanekp
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Re: Open Source Logic Analyzer Experiments

Post by vanekp » Fri May 17, 2019 5:19 pm

okay so that creates a file but cant even run it in ubuntu :-
# decode6502 --help
sh: 6: decode6502: not found
and certainly does not create a windows exe which I would prefer as I am no fan of Linux I always seem to fight with it...its frustrating :x
Peter.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Fri May 17, 2019 5:30 pm

vanekp wrote:
Fri May 17, 2019 5:19 pm
okay so that creates a file but cant even run it in ubuntu :-
# decode6502 --help
In the bash shell, try:

Code: Select all

./decode6502 --help

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vanekp
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Re: Open Source Logic Analyzer Experiments

Post by vanekp » Fri May 17, 2019 6:18 pm

okay have eventually got a windows exe that looks like its working as i get the following with a help switch :-

Code: Select all

C:\cygwin64\home\peter\6502Decoder>decode6502.exe --help
Usage: decode6502 [OPTION...] [FILENAME]

Decoder for 6502/65C02 logic analyzer capture files.

FILENAME must be a binary capture file with 16 bit samples.

If FILENAME is omitted, stdin is read instead.

The default bit assignments for the input signals are:
 - data: bit  0 (assumes 8 consecutive bits)
 -  rnw: bit  8
 - sync: bit  9
 -  rdy: bit 10
 - phi2: bit 11
 -  rst: bit 14

To specify that an input is unconnected, include the option with an empty
BITNUM. e.g. --sync=

If phi2 is not connected the capture file should contain one sample per
falling edge of phi2.

If rdy is not connected a value of '1' is assumed.

If sync is not connected a heuristic based decoder is used. This works well,
but can take several instructions to lock onto the instruction stream.
Use of sync, is preferred.

If RST is not connected, an alternative is to specify the reset vector:
 - D9CD (D9 is the high byte, CD is the low byte)
 - A9D9CD (optionally, also specify the first opcode, LDA # in this case)


  -a, --address              Show address of instruction.
  -b, --byte                 Byte samples
      --bbctube              Decode BBC tube protocol
  -c, --c02                  Enable 65C02 mode.
      --data=BITNUM          The start bit number for data
  -d, --debug=LEVEL          Sets debug level (0 1 or 2)
  -e, --emulate              Enable emulation, for error checking.
  -f, --bbcfwa               Show BBC floating poing work areas.
  -h, --hex                  Show hex bytes of instruction.
  -i, --instruction          Show instruction.
  -m, --machine=MACHINE      Enable machine specific behaviour
      --phi2[=BITNUM]        The bit number for phi2, blank if unconnected
  -p, --profile[=PARAMS]     Profile code execution.
  -q, --quiet                Set all the show options to off.
      --rdy[=BITNUM]         The bit number for rdy, blank if unconnected
      --rnw[=BITNUM]         The bit number for rnw
      --rst[=BITNUM]         The bit number for rst, blank if unconnected
  -r, --rockwell             Enable additional rockwell instructions.
      --sync[=BITNUM]        The bit number for sync, blank if unconnected
  -s, --state                Show register/flag state.
  -t, --trigger=ADDRESS      Trigger on address.
  -u, --undocumented         Enable undocumented 6502 opcodes (currently
                             incomplete)
      --vecrst[=HEX]         The reset vector, black if not known
  -y, --cycles               Show number of bus cycles.
  -?, --help                 give this help list
      --usage                give a short usage message
  -V, --version              print program version

Mandatory or optional arguments to long options are also mandatory or optional
for any corresponding short options.

Report bugs to <dave@hoglet.com>.
but get no output if I try using it on one of the included reset.bin out of the test folder with the following :-
decode6502.exe -h -s --sync= <reset.bin >data.txt
I end up with a zero byte txt file, guess more playing around is required.
Peter.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Fri May 17, 2019 7:10 pm

vanekp wrote:
Fri May 17, 2019 6:18 pm
I end up with a zero byte txt file, guess more playing around is required.
No output typically means an issue with clocking.

How exactly did you create the capture file? i.e. what signals are connected, and how was it clocked?

There are two options for clocking:
1. You capture syncronously (one sample per clock period), and pass in --phi2=
2. You capture asyncronously (several cycles per clock period), and pass in --phi2=<N> where N is the data bit that the clock signal is connected to

If you zip up the capture file, and post it I'll take a quick look.

Dave
Last edited by hoglet on Fri May 17, 2019 7:18 pm, edited 3 times in total.

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vanekp
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Re: Open Source Logic Analyzer Experiments

Post by vanekp » Fri May 17, 2019 9:40 pm

hoglet wrote:
Fri May 17, 2019 7:10 pm
vanekp wrote:
Fri May 17, 2019 6:18 pm
I end up with a zero byte txt file, guess more playing around is required.
No output typically means an issue with clocking.

How exactly did you create the capture file? i.e. what signals are connected, and how was it clocked?

There are two options for clocking:
1. You capture syncronously (one sample per clock period), and pass in --phi2=
2. You capture asyncronously (several cycles per clock period), and pass in --phi2=<N> where N is the data bit that the clock signal is connected to

If you zip up the capture file, and post it I'll take a quick look.

Dave
Hi Dave,

No as I said "one of the included reset.bin out of the test folder" (6502Decoder-master\test\beeb\reset.bin) so I used one of those just to test it but of cause I don't know how those bin files where made but figured it should work with it.

I assume this will also work with my LA5016 logic analyzer?

Sorry about the confusion, and thanks for you help.
Peter.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Fri May 17, 2019 9:49 pm

vanekp wrote:
Fri May 17, 2019 6:18 pm

but get no output if I try using it on one of the included reset.bin out of the test folder with the following :-
decode6502.exe -h -s --sync= <reset.bin >data.txt
I end up with a zero byte txt file, guess more playing around is required.
Should that not be:

Code: Select all

decode6502.exe -h -s --sync= reset.bin >data.txt
instead of :

Code: Select all

decode6502.exe -h -s --sync= <reset.bin >data.txt
i.e. no stdin redirect '<' in front of reset.bin ?

Edit: Okay I see help says it will read stdin if nothing specified, but still makes the '<' unrequired at best, and confusing it at worst. Been a while since I used it.
Last edited by Elminster on Fri May 17, 2019 9:51 pm, edited 2 times in total.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Sat May 18, 2019 6:40 am

All of the data in the test folder was synchronously sampled.

So you definitely need the following option:

Code: Select all

--phi2=
Try the following:

Code: Select all

decode6502.exe --phi2= -s -h -y  reset.bin >reset.txt
(the order of the option flags doesn't matter)

Dave
Last edited by hoglet on Sat May 18, 2019 6:40 am, edited 1 time in total.

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vanekp
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Re: Open Source Logic Analyzer Experiments

Post by vanekp » Sat May 18, 2019 6:26 pm

Okay that worked now that I know it works and have an idea how to use it, I can see if I can get it to work with some output from my Analyzer now.

Analyzer Output
Analyzer Output.png
and decoded6502 Output

Code: Select all

???? :          : RESET !!       : 7 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
D9CD : A9 40    : LDA #40        : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9CF : 8D 00 0D : STA 0D00       : 4 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D2 : 78       : SEI            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D3 : D8       : CLD            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
D9D4 : A2 FF    : LDX #FF        : 2 : A=40 X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
D9D6 : 9A       : TXS            : 2 : A=40 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9D7 : AD 4E FE : LDA FE4E       : 4 : A=80 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9DA : 0A       : ASL A          : 2 : A=00 X=FF Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=1
D9DB : 48       : PHA            : 3 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9DC : F0 09    : BEQ D9E7       : 3 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9E7 : A2 04    : LDX #04        : 2 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9E9 : 86 01    : STX 01         : 3 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9EB : 85 00    : STA 00         : 3 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9ED : A8       : TAY            : 2 : A=00 X=04 Y=00 SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9EE : 91 00    : STA (00),Y     : 6 : A=00 X=04 Y=00 SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9F0 : C5 01    : CMP 01         : 3 : A=00 X=04 Y=00 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F2 : F0 09    : BEQ D9FD       : 2 : A=00 X=04 Y=00 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F4 : C8       : INY            : 2 : A=00 X=04 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
D9F5 : D0 F7    : BNE D9EE       : 3 : A=00 X=04 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
D9EE : 91 00    : STA (00),Y     : 6 : A=00 X=04 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
D9F0 : C5 01    : CMP 01         : 3 : A=00 X=04 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F2 : F0 09    : BEQ D9FD       : 2 : A=00 X=04 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F4 : C8       : INY            : 2 : A=00 X=04 Y=02 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
D9F5 : D0 F7    : BNE D9EE       : 3 : A=00 X=04 Y=02 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
.
.
.
.
D9EE : 91 00    : STA (00),Y     : 6 : A=00 X=7F Y=FF SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F0 : C5 01    : CMP 01         : 3 : A=00 X=7F Y=FF SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F2 : F0 09    : BEQ D9FD       : 2 : A=00 X=7F Y=FF SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F4 : C8       : INY            : 2 : A=00 X=7F Y=00 SP=FE N=0 V=? D=0 I=1 Z=1 C=0
D9F5 : D0 F7    : BNE D9EE       : 2 : A=00 X=7F Y=00 SP=FE N=0 V=? D=0 I=1 Z=1 C=0
D9F7 : C8       : INY            : 2 : A=00 X=7F Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
D9F8 : E8       : INX            : 2 : A=00 X=80 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9F9 : E6 01    : INC 01         : 5 : A=00 X=80 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9FB : 10 F1    : BPL D9EE       : 2 : A=00 X=80 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D9FD : 8E 8E 02 : STX 028E       : 4 : A=00 X=80 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
DA00 : 8E 84 02 : STX 0284       : 4 : A=00 X=80 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
DA03 : A2 0F    : LDX #0F        : 2 : A=00 X=0F Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
DA05 : 8E 42 FE : STX FE42       : 4 : A=00 X=0F Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
DA08 : CA       : DEX            : 2 : A=00 X=0E Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=0E Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=0
DA0C : E0 09    : CPX #09        : 2 : A=00 X=0E Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0E : B0 F8    : BCS DA08       : 3 : A=00 X=0E Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA08 : CA       : DEX            : 2 : A=00 X=0D Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=0D Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0C : E0 09    : CPX #09        : 2 : A=00 X=0D Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0E : B0 F8    : BCS DA08       : 3 : A=00 X=0D Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA08 : CA       : DEX            : 2 : A=00 X=0C Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=0C Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0C : E0 09    : CPX #09        : 2 : A=00 X=0C Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0E : B0 F8    : BCS DA08       : 3 : A=00 X=0C Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA08 : CA       : DEX            : 2 : A=00 X=0B Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=0B Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0C : E0 09    : CPX #09        : 2 : A=00 X=0B Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0E : B0 F8    : BCS DA08       : 3 : A=00 X=0B Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA08 : CA       : DEX            : 2 : A=00 X=0A Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=0A Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0C : E0 09    : CPX #09        : 2 : A=00 X=0A Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0E : B0 F8    : BCS DA08       : 3 : A=00 X=0A Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA08 : CA       : DEX            : 2 : A=00 X=09 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=09 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0C : E0 09    : CPX #09        : 2 : A=00 X=09 Y=01 SP=FE N=0 V=? D=0 I=1 Z=1 C=1
DA0E : B0 F8    : BCS DA08       : 3 : A=00 X=09 Y=01 SP=FE N=0 V=? D=0 I=1 Z=1 C=1
DA08 : CA       : DEX            : 2 : A=00 X=08 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA09 : 8E 40 FE : STX FE40       : 4 : A=00 X=08 Y=01 SP=FE N=0 V=? D=0 I=1 Z=0 C=1
DA0C : E0 09    : CPX #09        : 2 : A=00 X=08 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
DA0E : B0 F8    : BCS DA08       : 2 : A=00 X=08 Y=01 SP=FE N=1 V=? D=0 I=1 Z=0 C=0
Now I have a base line so if I ever have a faulty BBC I have something to compare it with :)
Thanks for you help Dave and for the useful Utility and Article :D
Last edited by vanekp on Sat May 18, 2019 11:59 pm, edited 1 time in total.
Peter.

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jms2
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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Tue Jul 02, 2019 7:39 pm

I have got hold of an FX2 board and I am working through the installation instructions for Windows from earlier in the thread.

Everything has worked fine up until the point where I try to compile 6502decode, at which point I get a lot of errors as shown below.

Dave have you got any ideas what might be wrong? Basically it seems to lack access to various references as far as I can see?

Code: Select all

$ gcc -Wall -O3 -o decode6502 src/main.c src/em_6502.c -l argp
/tmp/cczC53lN.o:main.c:(.text+0x484): undefined reference to `profiler_profile_instruction'
/tmp/cczC53lN.o:main.c:(.text+0x484): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `profiler_profile_instruction'
/tmp/cczC53lN.o:main.c:(.text+0xc87): undefined reference to `profiler_parse_opt'
/tmp/cczC53lN.o:main.c:(.text+0xc87): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `profiler_parse_opt'
/tmp/cczC53lN.o:main.c:(.text.startup+0x19c): undefined reference to `profiler_done'
/tmp/cczC53lN.o:main.c:(.text.startup+0x19c): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `profiler_done'
/tmp/cczC53lN.o:main.c:(.text.startup+0x1ab): undefined reference to `profiler_init'
/tmp/cczC53lN.o:main.c:(.text.startup+0x1ab): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `profiler_init'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x63a): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x63a): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xa0d): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xa0d): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xba9): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xba9): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xc39): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xc39): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xcc9): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xcc9): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xd49): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xd49): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xde9): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xde9): additional relocation overflows omitted from the output
/tmp/cclhAVnO.o:em_6502.c:(.text+0xe89): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xf4c): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x105c): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x11df): more undefined references to `tube_read' follow
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1ab8): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1c59): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1ce4): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1f1a): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1fda): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x2429): undefined reference to `tube_read'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x2a84): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xa90): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xb10): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0xf80): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1090): undefined reference to `tube_write'
/tmp/cclhAVnO.o:em_6502.c:(.text+0x1236): more undefined references to `tube_write' follow
collect2: error: ld returned 1 exit status

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Tue Jul 02, 2019 7:55 pm

Panic over - I tried the previously suggested

Code: Select all

bash build.sh
...and whilst it didn't work the first time, it did work the second time (?!)

So now I have a Windows executable.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 8:09 am

I have got it all plugged in now, but there is one final hurdle... which is that it doesn't seem to be capturing any data.

If I understand the instructions correctly, the command ...

sigrok-cli -d fx2lafw --config samplerate=12MHz:captureratio=1 -o data.bin -O binary --triggers D14=r --samples=12M -w

...shouldn't exit unless it captures something, but if I issue the command and then don't switch on the Beeb, it does exit after a few seconds (without generating an error).

If I do get in quick and switch on the Beeb while the command is still running, it doesn't make any difference (ie, I still don't get anything).

Pulseview does seem to capture the Beeb's activity though, so the logic analyser does seem to be working.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Wed Jul 03, 2019 8:16 am

Been a while sin I used the cli but could it be it is not finding the device and you need to tell it where to find it or you maybe talking at wrong speed etc.

e.g. from page 1 of the thread

Code: Select all

ols:conn=/dev/ttyUSB1:serialcomm=921600/8n1

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Jul 03, 2019 8:23 am

Elminster wrote:
Wed Jul 03, 2019 8:16 am
Been a while sin I used the cli but could it be it is not finding the device and you need to tell it where to find it or you maybe talking at wrong speed etc.

e.g. from page 1 of the thread

Code: Select all

ols:conn=/dev/ttyUSB1:serialcomm=921600/8n1
That shouldn't be necessary with the FX2 logic analyser - it relates to other logic analyzers (like the Papilo one).

Dave
Last edited by hoglet on Wed Jul 03, 2019 8:24 am, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Jul 03, 2019 8:24 am

jms2 wrote:
Wed Jul 03, 2019 8:09 am
If I understand the instructions correctly, the command ...

sigrok-cli -d fx2lafw --config samplerate=12MHz:captureratio=1 -o data.bin -O binary --triggers D14=r --samples=12M -w

...shouldn't exit unless it captures something, but if I issue the command and then don't switch on the Beeb, it does exit after a few seconds (without generating an error).
Indeed, that command should wait for a rising edge on D14 as a trigger (which I assume you have connected to reset).

Do you have ground connected correctly?

Can you detail the connections you have made, and ideally post a couple of photos?

Is a data.bin fine generated? What length is it?

Dave

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 8:55 am

I have GND connected to pin 1 (just visible as a white wire in the first photo). At the fx2 board there are several pins marked GND so I picked one at random - does this matter? The one I used is next to SCL.

It does generate a BIN file but of zero bytes.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 9:07 am

hoglet wrote:
Wed Jul 03, 2019 8:24 am
Indeed, that command should wait for a rising edge on D14 as a trigger (which I assume you have connected to reset).
That might be the issue. I have connected the wires up as per the list from earlier in this thread, but in that list NRST is listed as being not used. I connected it anyway as shown, but I can't figure out how that relates to D14?

Tube Connector -> Logic Analyzer
------------- --------------
Pin 1 (0V) -> GND
Pin 2 (RnW) -> PD0
Pin 4 (2MHzE) -> PD3
Pin 6 (NIRQ) -> PD4
Pin 8 (NTUBE) -> PD7 (not actually used yet)
Pin 10 (NRST) -> PD6 (not actually used yet)
Pin 12 (D0) -> PB0
Pin 14 (D1) -> PB1
Pin 16 (D2) -> PB2
Pin 18 (D3) -> PB3
Pin 20 (D4) -> PB4
Pin 22 (D5) -> PB5
Pin 24 (D6) -> PB6
Pin 26 (D7) -> PB7

I will attach a couple of photos in the next post.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 9:08 am

Photos of connections
Attachments
DEFF8A2D-7714-47CD-AFE1-73BE7B1CE304.jpeg
E8E23779-AD78-48F7-8098-045D32ADBD60.jpeg

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Wed Jul 03, 2019 9:11 am

hoglet wrote:
Wed Jul 03, 2019 8:23 am
Elminster wrote:
Wed Jul 03, 2019 8:16 am
Been a while sin I used the cli but could it be it is not finding the device and you need to tell it where to find it or you maybe talking at wrong speed etc.

e.g. from page 1 of the thread

Code: Select all

ols:conn=/dev/ttyUSB1:serialcomm=921600/8n1
That shouldn't be necessary with the FX2 logic analyser - it relates to other logic analyzers (like the Papilo one).

Dave
Well it has been a while

@JMS2 have you considered Myelin's FX2 Logic analyser piggyback board at a later date, it makes life so much easier without needing all the jumper wires.

https://github.com/google/myelin-acorn- ... ge_adapter
Last edited by Elminster on Wed Jul 03, 2019 9:13 am, edited 2 times in total.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 9:15 am

Elminster wrote:
Wed Jul 03, 2019 9:11 am
JMS have you considered Myelin FX2 Logic analyser piggyback board at a later date, it makes life so much easier without needing all the jumper wires.
Yes, I'm aware there are easier ways to make the connections, but what I'm doing here with the Tube connector is only to validate that the whole thing is working. Once I've done that, I intend to use test hooks to connect this to something else!

That said, this system looks to be very useful so I may well get something more functional for diagnosing Beeb issues in future.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Wed Jul 03, 2019 9:19 am

jms2 wrote:
Wed Jul 03, 2019 9:15 am
Elminster wrote:
Wed Jul 03, 2019 9:11 am
JMS have you considered Myelin FX2 Logic analyser piggyback board at a later date, it makes life so much easier without needing all the jumper wires.
That said, this system looks to be very useful so I may well get something more functional for diagnosing Beeb issues in future.
That usually happens the first time you want to compare the results of a couple of different machines :)

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Jul 03, 2019 9:33 am

What I would suggest is to delete the trigger option for now.

Try the following tests:

1. Disconnect the logic analyzer from the PC and run:

Code: Select all

sigrok-cli -d fx2lafw --config samplerate=12MHz:captureratio=1 -o data.bin -O binary --samples=12M -w
You should get a error:

Code: Select all

No devices found.
2. Connect the logic analyzer to the PC's USB port and run the same command:

Code: Select all

sigrok-cli -d fx2lafw --config samplerate=12MHz:captureratio=1 -o data.bin -O binary --samples=12M -w
That should exit after 1-2 seconds and have created a 24MB data.bin file.

No jumpers are required for this to work (leave them connected, with the Beeb off for now)

This should verify whether the sigrok drivers have been correctly installed.

Dave

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 9:46 am

hoglet wrote:
Wed Jul 03, 2019 9:33 am
1. Disconnect the logic analyzer from the PC and run:

Code: Select all

sigrok-cli -d fx2lafw --config samplerate=12MHz:captureratio=1 -o data.bin -O binary --samples=12M -w
You should get a error:

Code: Select all

No devices found.
Yes I do.
2. Connect the logic analyzer to the PC's USB port and run the same command:

Code: Select all

sigrok-cli -d fx2lafw --config samplerate=12MHz:captureratio=1 -o data.bin -O binary --samples=12M -w
That should exit after 1-2 seconds and have created a 24MB data.bin file.
Kind of. What I actually get is a 3,408K data.bin file. (EDIT: containing the bytes 00, 67 repeatedly).

For what it's worth, just before doing the above test I set up PulseView so that D14 was the trigger and switched on the Beeb. I got this (which to the untrained eye looks promising):
Capture.JPG
Last edited by jms2 on Wed Jul 03, 2019 9:47 am, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Jul 03, 2019 9:51 am

jms2 wrote:
Wed Jul 03, 2019 9:46 am
Kind of. What I actually get is a 3,408K data.bin file. (EDIT: containing the bytes 00, 67 repeatedly).
Hmm, it does seem there is an issue with sigrok on your machine.

For some reason the capture is stopping early, probably due to data loss on the USB connection.

What age of PC/Laptop is it?

Is the USB port definitely USB2 capable?

(Although you can see changing waveforms in Pulseview, what you can't see is whether there has been any data loss. Also, in pulseviw you have the capture rate set to 20KHz. It needs to be 12MHz!)

Dave
Last edited by hoglet on Wed Jul 03, 2019 9:52 am, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 10:11 am

Good point about the capture rate - when I set it to 12MHz, I get nothing at all. In fact, Pulseview drops out of "run" mode within a second or so, just like sigrok-cli :(

The machine certainly has USB2.0 ports but it is fairly old - about 5 years I would say. It has an Intel Core i5-2410M processor running at 2.3 GHz.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 10:15 am

I found that Pulseview works fine for speeds up to 8MHz.

However, if I shift the FX2 round to a USB port on the right hand side of the machine, PulseView works at 12Mhz!

Now to try the CLI version.

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Re: Open Source Logic Analyzer Experiments

Post by jms2 » Wed Jul 03, 2019 10:22 am

This nearly works!

I get 24,000,000 bytes of data.
This equates to 560,610 instructions captured (seems like not quite enough).
I get 1 decoder failure (should be 0)

The decoded data has a hint of rightness about it, but is basically corrupt:

???? : : RESET !! : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
A9D9 : 40 : RTI : A=?? X=?? Y=?? SP=?? N=0 V=0 D=1 I=1 Z=0 C=1
7840 : D8 : CLD : A=?? X=?? Y=?? SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
7841 : A2 A2 : LDX #A2 : A=?? X=A2 Y=?? SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
7843 : FF : ??? : A=?? X=A2 Y=?? SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
7844 : 9A : TXS : A=?? X=A2 Y=?? SP=A2 N=1 V=0 D=0 I=1 Z=0 C=1
7845 : AD 4E FE : LDA FE4E : A=80 X=A2 Y=?? SP=A2 N=1 V=0 D=0 I=1 Z=0 C=1
7848 : 0A : ASL A : A=00 X=A2 Y=?? SP=A2 N=0 V=0 D=0 I=1 Z=1 C=1
7849 : 48 : PHA : A=00 X=A2 Y=?? SP=A1 N=0 V=0 D=0 I=1 Z=1 C=1

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