New SCSI Host Adaptor

[dp11]

I think this is already implemented in the code?

Code: Select all

	// SCSI device databus bidirectional control
	wire [7:0] scsi_nDATA_in;
	wire [7:0] scsi_nDATA_out;
	
	// Here the input and output of the databus needs to be tied together
	// since the Acorn SCSI host adapter will drive the BBC databus output
	// latch from the data in latch if the SCSI bus isn't driven (this is 
	// used by ADFS to detect the presence of the host adapter, so we have
	// to emulate it even if the logic isn't needed for the SCSI).
	assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;
	assign scsi_nDATA_in = (~scsi_InO) ? scsi_nDATA : scsi_nDATA_out;

Does that look right?

The above doesn't make the databus open collector. Remember for open collector the bus isn't driven when you need a "1" on the pin.

[KenLowe]

Instead of this line:

Code: Select all

    assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;

I think you need something like:

Code: Select all

    assign scsi_nDATA[7] = (scsi_InO & ~scsi_nDATA_out[7]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[6] = (scsi_InO & ~scsi_nDATA_out[6]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[5] = (scsi_InO & ~scsi_nDATA_out[5]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[4] = (scsi_InO & ~scsi_nDATA_out[4]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[3] = (scsi_InO & ~scsi_nDATA_out[3]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[2] = (scsi_InO & ~scsi_nDATA_out[2]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[1] = (scsi_InO & ~scsi_nDATA_out[1]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[0] = (scsi_InO & ~scsi_nDATA_out[0]) ? 1'b0 : 1'bZ;

I can't think of a way to achieve this with a single line!

(Hopefully the Xilinx tools won't barf at multiple assignments like this}

Dave

Thanks. It was ok with that modification.

I think this is already implemented in the code?

Code: Select all

	// SCSI device databus bidirectional control
	wire [7:0] scsi_nDATA_in;
	wire [7:0] scsi_nDATA_out;
	
	// Here the input and output of the databus needs to be tied together
	// since the Acorn SCSI host adapter will drive the BBC databus output
	// latch from the data in latch if the SCSI bus isn't driven (this is 
	// used by ADFS to detect the presence of the host adapter, so we have
	// to emulate it even if the logic isn't needed for the SCSI).
	assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;
	assign scsi_nDATA_in = (~scsi_InO) ? scsi_nDATA : scsi_nDATA_out;

Does that look right?

The above doesn't make the databus open collector. Remember for open collector the bus isn't driven when you need a "1" on the pin.

Ok. That's my lack of understanding. I thought that 8'hZZ was switching to open collector.

[hoglet]

Ken,

If you post the updated CPLD fitter report, I can check the logic equations for the open collector outputs look correct.

They should all follow this pattern:

Code: Select all

XXXX_I <= '0';
XXXX <= XXXX_I when XXXX_OE = '1' else 'Z';
XXXX_OE <= XXXX;

Dave

[cmorley]

Oh I remembered about the open collector then forgot when I posted. What hoglet wrote!

Verilog does have synthisisable for loops but you don't really need that for 8 lines.

edit: in case you do though you do it along these lines. code pinched from another forum...

Code: Select all

integer i;
reg [7:0] io_internal;

always @(variable)
for (i=0;i<8;i=i+1) io_internal[i] = variable[i]?1'b0:1'bz;

assign io = io_internal;

[dp11]

I think this is already implemented in the code?

Code: Select all

	// SCSI device databus bidirectional control
	wire [7:0] scsi_nDATA_in;
	wire [7:0] scsi_nDATA_out;
	
	// Here the input and output of the databus needs to be tied together
	// since the Acorn SCSI host adapter will drive the BBC databus output
	// latch from the data in latch if the SCSI bus isn't driven (this is 
	// used by ADFS to detect the presence of the host adapter, so we have
	// to emulate it even if the logic isn't needed for the SCSI).
	assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;
	assign scsi_nDATA_in = (~scsi_InO) ? scsi_nDATA : scsi_nDATA_out;

Does that look right?

The above doesn't make the databus open collector. Remember for open collector the bus isn't driven when you need a "1" on the pin.

Ok. That's my lack of understanding. I thought that 8'hZZ was switching to open collector.
[/quote]

Sort off the 8'hzz stops driving the bus , but on when scsi_InO is low . When scsi_InO is high the databus is driven by scsi_nDATA_out. So if a bit in scsi_nDATA_out is a "1" a "1" would be driven on that bit.

Code: Select all

	// SCSI device databus bidirectional control
	wire [7:0] scsi_nDATA_in;
	wire [7:0] scsi_nDATA_out;
	
	// Here the input and output of the databus needs to be tied together
	// since the Acorn SCSI host adapter will drive the BBC databus output
	// latch from the data in latch if the SCSI bus isn't driven (this is 
	// used by ADFS to detect the presence of the host adapter, so we have
	// to emulate it even if the logic isn't needed for the SCSI).
	assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;
	assign scsi_nDATA_in = (~scsi_InO) ? scsi_nDATA : scsi_nDATA_out;

Also I'm not sure the last line matches the real hardware . In the original design Reads always come from what is actually on the bus and so should be :

Code: Select all

	assign scsi_nDATA_in = scsi_nDATA ;

This means if the there is a bit error on the actual cable it can be detected.

They may be other changes which make the above invalid.

[KenLowe]

Ok, guys. I've had some success with the following changes:

• SEL, ACK and RST now open collector outputs
• Slew rate on all the outputs set to SLOW

I can now switch into the FORMAT directory without error, and can load the files from that directory without error. Not been brave enough to try a save yet!

I did initially try with databus set to open collector, but it wasn't working, so I switched that back to original configuration, and that is what is now working. That said, this is on a board where I've completely removed the SCSI termination.

Ken,

If you post the updated CPLD fitter report, I can check the logic equations for the open collector outputs look correct.

They should all follow this pattern:

Code: Select all

XXXX_I <= '0';
XXXX <= XXXX_I when XXXX_OE = '1' else 'Z';
XXXX_OE <= XXXX;

Dave

I'll post up 2 CPLD fitter reports shortly. One with the current working configuration, and one with the modified databus open collector outputs that's currently not working.

Edit: So a save has completely broken the drive! I'll need to rewrite the FSM & Root directory...

[hoglet]

Ken,

Is there also some kind of termination at the far end of the SCSI bus, either on the drive or at the end of the cable?

(SCSI-1 is designed to have termination at both ends, because data can flow in either direction)

Dave

[KenLowe]

Ken,

Is there also some kind of termination at the far end of the SCSI bus, either on the drive or at the end of the cable?

(SCSI-1 is designed to have termination at both ends, because data can flow in either direction)

Dave

Yes. The drive end has termination in the form of a resistor pack.

I'm currently trying to get floppy drive working again on this machine to get the utilities to reformat the HDD. I'm getting a stupid 'Bad String' error on boot!

[KenLowe]

The DFS 'Bad String' turned out to be a corrupt ROM. HDD is now back in action. I've also soldered the 330R GND resistors back onto the board, so I've got full SCSI termination on the board again. That took a bit of effort!

Disk reads still seem to be working fine now with the open collector on the SEL, ACK & RST lines, but writing remains a bit marginal. I'm going to reflash the CPLD with the open collector databus configuration again, and see if that works better now that I've got the full SCSI termination implemented again.

In the interim, I've attached 2 reports. One is with open collector on the SEL, ACK & RST lines. The other is with open collector on the SEL, ACK, RST & databus lines:

CPLD Report - OC Control.txt

Open collector on the SEL, ACK & RST lines

(59.32 KiB) Downloaded 21 times

CPLD Report - OC ControlData.txt

Open collector on the SEL, ACK, RST & databus lines

(61.5 KiB) Downloaded 24 times

Edit: It still doesn't work with the open collector databus configuration. It just hangs after printing Acorn ADFS on Boot. It doesn't get to the basic '>' prompt.

[KenLowe]

Picking this up again today, and I still can't get it to work. When starting to dig in a bit further, I'm getting myself really confused.

Instead of this line:

Code: Select all

    assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;

I think you need something like:

Code: Select all

    assign scsi_nDATA[7] = (scsi_InO & ~scsi_nDATA_out[7]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[6] = (scsi_InO & ~scsi_nDATA_out[6]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[5] = (scsi_InO & ~scsi_nDATA_out[5]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[4] = (scsi_InO & ~scsi_nDATA_out[4]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[3] = (scsi_InO & ~scsi_nDATA_out[3]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[2] = (scsi_InO & ~scsi_nDATA_out[2]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[1] = (scsi_InO & ~scsi_nDATA_out[1]) ? 1'b0 : 1'bZ;
    assign scsi_nDATA[0] = (scsi_InO & ~scsi_nDATA_out[0]) ? 1'b0 : 1'bZ;

I'm probably not understanding the code correctly. However, isn't this the data bus output code that needs to be open collector (note, I think the reference to 74LS03 should actually be 74LS38) instead of the code above:

Code: Select all

	// The Q output from the data in latch is connected to two 74LS03 ICs in the Acorn
	// host adapter (quad 2 input NAND gates with open-collector outputs).  This acts
	// to invert the Q output as well as acting as a 'output enable' to tristate the 
	// output to the SCSI databus.  Rather than implement 8 NAND gates individually, here
	// we combine them into a single verilog module for convenience.
	//
	// For the AIV host adapter the functionality is the same with the exception that
	// the AIV does not invert the output databus.
	//
	// The Output Enable (2nd input to the NAND gates) is supplied by the scsi_InO signal.
	inverterWithOutputEnable scsiOutputInverter(
		.D(dataInLatchQ),
		.OE(scsi_InO),
		.nInvertFlag(bbc_INTnEXT),
		.Q(scsi_nDATA_out)
	);

Where inverterWithOutputEnable is driven by:

Code: Select all

module inverterWithOutputEnable(
    input [7:0] D,
    input OE,
	 input nInvertFlag,
    output [7:0] Q
    );

	// If we are connected to the external bus D should be inverted, if connected
	// to the internal bus D should not be inverted
	wire [7:0] data;
	assign data = (nInvertFlag) ? D : ~D;

	// If output is enabled, Q = data otherwise Q = 0.
	// If output is disabled we should high-Z, but since the module
	// is buried we have to rely on the bidirectional control to implement
	// high-Z
	assign Q = (OE) ? data : 8'b0;

endmodule

Does this mean that the SCSI data bus is already open collector??? If not, any further words of wisdom???

[dp11]

For a normal bus you need three conditons for each bit

1) HighZ ( not driving the bus )
2) Logic zero
3) Logic one

condition 1 is usually used to stop driving the bus to enable the other end to drive the bus ( e.g. all 8 bits aren't driving)

For your open collector bus you also in the same order need the following conditions

1) High Z ( not driving the bus )
2) Logic zero
3) High Z ( something else pulls the bit high)

condition 1 is usually used to stop driving the bus to enable the other end to drive the bus ( e.g. all 8 bits aren't driving)
condition 3 is done on a bit by bit bases as some bits in a bit might be a '0' and others might be in effect a '1' via the open collector

The code doesn't do open collector it does normal bus so you need hoglets suggestion if you want an Open collector data bus.

[KenLowe]

Success! Loading and saving is now working without any errors.

Earlier today I received a couple of 2x25 pin sockets for my SCSI host adaptor to SCSI drive connector board, so I soldered those up this evening, and replaced my dupont based 'SCSI' cable with the connector board, and it just worked!

In the Verilog code, I've retained the modified logic for open collector outputs on the ACK, SEL & RST lines, but left the databus logic unchanged.

Thanks very much for your help and encouragement. I would have struggled without it. You guys rock!!!!

Still want to do a bit of further testing but, in the interim, here's a couple of photos of the working setup :

Test with 1st drive

Test with 2nd drive

Test with 2nd drive - with close up of connector board

Drives with old and new SCSI host adaptors side by side

Some ROM images saved from my IntegraB board to the SCSI drive

[KenLowe]

For a normal bus you need three conditons for each bit

1) HighZ ( not driving the bus )
2) Logic zero
3) Logic one

condition 1 is usually used to stop driving the bus to enable the other end to drive the bus ( e.g. all 8 bits aren't driving)

For your open collector bus you also in the same order need the following conditions

1) High Z ( not driving the bus )
2) Logic zero
3) High Z ( something else pulls the bit high)

condition 1 is usually used to stop driving the bus to enable the other end to drive the bus ( e.g. all 8 bits aren't driving)
condition 3 is done on a bit by bit bases as some bits in a bit might be a '0' and others might be in effect a '1' via the open collector

The code doesn't do open collector it does normal bus so you need hoglets suggestion if you want an Open collector data bus.

Hi Dominic. Thanks for the explanation. I do understand the open collector concept (although I didn't fully appreciate the difference between conditions 1 & 3 that you refer to above), but was struggling with the implementation in Verilog. Unfortunately the suggestion that hoglet offered didn't work for me. It just caused the beeb to hang when ADFS was trying to communicate with the drive. That is why I ended up looking at the databus code a bit further, and noted the comments about buried code impacting high-Z.

Anyway, as mentioned in my previous post, I've managed to get the drive working reliably without modifying the databus logic. I think the main issue I was having was with the home made SCSI cable. Once I replaced that with a more robust link it all started to work.

[dp11]

Might be worth trying hoglets code again with the new cable.

[cmorley]

Driving the databus push-pull, and only going high-z to disconnect, will likely work fine because with the 3v3 VIO the output will be pulling up the 2.85v passive SCSI termination voltage towards 3v3. You could work out (or measure) by how much.

I don't know what the spec is for high voltage tolerance on the SCSI I bus but I'm be surprised if 3v3 is not still safe. Open collector is technically correct by the sounds of it and only 4 or 5 lines of code in verilog for an n bit wide bus like I showed above (post edit).

The output low voltage is still the key. Did you 'scope that? You really want to be down at the 0.2v for reliable signalling as hoglet explained.

[KenLowe]

The output low voltage is still the key. Did you 'scope that? You really want to be down at the 0.2v for reliable signalling as hoglet explained.

Here's some scoping results, looking at SCSI data bus bit 0:

Ctrl-Break

*DIR ROMS

*LOAD ADFS130 3000

[KenLowe]

Might be worth trying hoglets code again with the new cable.

Tried that again earlier. Got some really strange graphical results on the beeb display with no signs of the normal boot up messages, so quickly reverted back.

As I mentioned earlier, I'm not convinced we're actually looking at the right piece of code here for driving the SCSI data bus pins (and therefore applying the open collector code to the wrong piece of logic), but happy to be guided otherwise.

[cmorley]

As hoglet predicted you are closer to 0.6-0.7v than 0.2v. This is greater than the 0.5v maximum output voltage for asserted signal and doesn't give you much margin to the 0.8v input threshold for asserted signal.

I would buffer it.

[hoglet]

Ken,

As I mentioned earlier, I'm not convinced we're actually looking at the right piece of code here for driving the SCSI data bus pins (and therefore applying the open collector code to the wrong piece of logic), but happy to be guided otherwise.

Any chance you could post your complete project (with the changes to make the data bus open collector)? It's easy for small errors to creep in un-noticed.

What's a little confusing in Simon's original design is that he does have a low level module called inverterWithOutputEnable, but it does not actually set the outputs to high impedence. This is the pertinent comment:

Code: Select all

 	// If output is enabled, Q = data otherwise Q = 0.
	// If output is disabled we should high-Z, but since the module
	// is buried we have to rely on the bidirectional control to implement
	// high-Z
	assign Q = (OE) ? data : 8'b0; 

What Simon is saying is that the implementation of the high-Z state should be in the parent module, which is exactly what we have done. The reason for this is because it's not possible in a CPLD to have a tristate signal internally. This can only be done right at the periphery, in the IO driver. That's generally why the logic to express this is placed in the top level module.

Looking at the scope plots, it does look like the "0" level is significantly raised. It looks more like 0.7V that 0.2V. That means there very much less immunity to noise, which I think is explains many of the symptoms you are seeing. There are also a couple of places where is seems to be raised even higher than this, though it's a bit difficult to see because you are zoomed out so much.

To be honest, whether or not the data bus uses open collector or conventional tristate logic is likely much less significant than the raised logic low level you are seeing in the scope plots.

I think the bottom line here is that you would be better of using seperate open collector drivers like the original design did, that are specified to be able to sink at least 48mA.

Dave

[KenLowe]

Just for reference here's the equivalent traces using my original Viglen host adaptor:

Ctrl-Break

*DIR ROMS

*LOAD ADFS130 3000

[dp11]

I've had a quick look but I can't find the specification for the maximum current in the Ground pin of CPLD. Might be worth checking you aren't exceeding it under the worst case. I notice the spare output pin are connected to ground. What you can do which might help slightly is set them to be outputs and drive them low.

The original adaptor signals look good.

[KenLowe]

Ken,

As I mentioned earlier, I'm not convinced we're actually looking at the right piece of code here for driving the SCSI data bus pins (and therefore applying the open collector code to the wrong piece of logic), but happy to be guided otherwise.

Any chance you could post your complete project (with the changes to make the data bus open collector)? It's easy for small errors to creep in un-noticed.

Here's the complete project with the modified data bus logic. This code builds ok, but it doesn't work on my test system. If I comment out the revised logic, and go back to the original data bus logic it works fine.

Thank you for looking.

[dominicbeesley]

Hi Ken,

I'm only getting a few stolen minutes here and there to look at this - please could you post up the version of SCSIAdapter.v that is working for you and I'll try and have a look, I can't keep track of what is going on here.

The stuff in the most recent zip looks close but I suspect that there is a problem with the data direction signal (or it is named confusingly!)

D

[KenLowe]

Hi Ken,

I'm only getting a few stolen minutes here and there to look at this - please could you post up the version of SCSIAdapter.v that is working for you and I'll try and have a look, I can't keep track of what is going on here.

The stuff in the most recent zip looks close but I suspect that there is a problem with the data direction signal (or it is named confusingly!)

D

Here's the working SCSIAdapter.v file. The working data bus logic is the original logic as written by Simon. The commented out logic is the suggested open collector change by hoglet that doesn't work for me:

Code: Select all

// Here the input and output of the databus needs to be tied together
// since the Acorn SCSI host adapter will drive the BBC databus output
// latch from the data in latch if the SCSI bus isn't driven (this is 
// used by ADFS to detect the presence of the host adapter, so we have
// to emulate it even if the logic isn't needed for the SCSI).
assign scsi_nDATA = (scsi_InO) ? scsi_nDATA_out : 8'hZZ;
// assign scsi_nDATA[7] = (scsi_InO & ~scsi_nDATA_out[7]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[6] = (scsi_InO & ~scsi_nDATA_out[6]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[5] = (scsi_InO & ~scsi_nDATA_out[5]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[4] = (scsi_InO & ~scsi_nDATA_out[4]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[3] = (scsi_InO & ~scsi_nDATA_out[3]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[2] = (scsi_InO & ~scsi_nDATA_out[2]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[1] = (scsi_InO & ~scsi_nDATA_out[1]) ? 1'b0 : 1'bz;
// assign scsi_nDATA[0] = (scsi_InO & ~scsi_nDATA_out[0]) ? 1'b0 : 1'bz;

[hoglet]

Here's the complete project with the modified data bus logic. This code builds ok, but it doesn't work on my test system. If I comment out the revised logic, and go back to the original data bus logic it works fine.

I couldn't actually compile the project myself, because it's missing the inverterWithOutputEnable.v file.

But I looked at the equations in the .rpt file, and they are as expected for open collector outputs.

So I'm at a bit of a loss as to why this change breaks things.

Dave

[dp11]

It look as though you have two pins scsi_INTnEXT scsi_nCONF which are outputs . On the Circuits these appear to be connected to pins which are grounded.

[KenLowe]

Here's the complete project with the modified data bus logic. This code builds ok, but it doesn't work on my test system. If I comment out the revised logic, and go back to the original data bus logic it works fine.

I couldn't actually compile the project myself, because it's missing the inverterWithOutputEnable.v file.

But I looked at the equations in the .rpt file, and they are as expected for open collector outputs.

So I'm at a bit of a loss as to why this change breaks things.

Dave

Oops. Sorry about that. Here's a copy of the project with inverterWithOutputEnable.v included.

Edit: Updated project file below...

[KenLowe]

It look as though you have two pins scsi_INTnEXT scsi_nCONF which are outputs . On the Circuits these appear to be connected to pins which are grounded.

Good spot. I've now fixed that.

[dp11]

Could you try the build again. If it doesn't work could I have the report file again.

[KenLowe]

Could you try the build again. If it doesn't work could I have the report file again.

Removing the scsi_INTnEXT & scsi_nCONF signals has definitely made a difference. The open collector data bus logic is no longer causing the beeb to do weird stuff on power up. I can now get to the '>' prompt. However, if I try to load a file, I then get the 'Broken Directory' error. Project files attached.