Atom 2k18 ?

discussion of games, software, hardware & emulators relating to the Acorn Atom and Acorn System machines.
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Re: Atom 2k18 ?

Post by roland » Sat Mar 09, 2019 5:40 pm

hoglet wrote:
Sat Mar 09, 2019 4:08 pm
The Mouse, if I remember correctly, is actually bidirectional.
IMHO powering the keyboard and the mouse with 5V is the most universal approach but the birectional mouse will make it difficult to adjust the levels. I'll have to search for a solutions (besides skipping the PS/2 interface....) :-k

I'll have a look at the Godil diagram how they solved that issue....
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Re: Atom 2k18 ?

Post by 1024MAK » Sat Mar 09, 2019 6:31 pm

With the PS/2 interface, both the data line and the clock line for both keyboard and mouse can be driven low by either the host or the device depending on the communications that are being attempted.

The keyboard device always drives the clock line with clock pulses during a data transmission or during data reception. But the host can drive it low to start a host to device communication.

If you don’t require to instruct the keyboard to change it’s LED indications, or change any of it’s modes, then there is no need for the host to drive the data or clock lines.

Modern keyboards often have two or three modes. This affects the codes that they send to the host.

As the PS/2 data and clock lines are open collector / open drain with pull-up resistors, I would not have thought that level shifting would be too much of a problem.

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Re: Atom 2k18 ?

Post by fordp » Sat Mar 09, 2019 9:57 pm

This looks interesting. I am not totally sure why you would run the memories at 5V however I would have thought running those at 3.3V would have saved a lot of complexity.
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Re: Atom 2k18 ?

Post by roland » Sat Mar 09, 2019 11:38 pm

Memories will run at 3.3V. Within a few days I will post the first draft of the schematic diagram.
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Re: Atom 2k18 ?

Post by fordp » Sun Mar 10, 2019 8:23 am

roland wrote:
Sat Mar 09, 2019 11:38 pm
Memories will run at 3.3V. Within a few days I will post the first draft of the schematic diagram.
Brilliant.
Just one more idea to save lots of pins at the expense of some logic gates but I would have thought the keyboard could be multiplexed on to the address and data bus with just maybe one pin used on the FPGA as a keyboard select.
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Re: Atom 2k18 ?

Post by roland » Sun Mar 10, 2019 10:11 am

fordp wrote:
Sun Mar 10, 2019 8:23 am
Just one more idea to save lots of pins at the expense of some logic gates but I would have thought the keyboard could be multiplexed on to the address and data bus with just maybe one pin used on the FPGA as a keyboard select.
Interesting proposal! When I only use one 74LVC244 I can connect the keyboard to the databus instead of eight dedicated I/O pins. It requires however one select signal for #B001 so this solution will free seven I/O pins. Hoglet, what are your thoughts about this? Can it free up some resources in the FPGA and what shall we do with the extra free pins?
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Re: Atom 2k18 ?

Post by roland » Sun Mar 10, 2019 11:30 am

Regarding the mouse interface I have looked at the Godil level shifters, but these are too complicated for my project. I have found another article for a simple interface at https://www.digikey.com/eewiki/pages/vi ... troduction. They only use a few resistors. Any thoughts about that solution?
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Re: Atom 2k18 ?

Post by bprosman » Sun Mar 10, 2019 11:44 am

Or this one, only requires 1 (SMD) transistor.
https://www.nxp.com/docs/en/application ... N10441.pdf

Its bi-directional.
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Re: Atom 2k18 ?

Post by fordp » Sun Mar 10, 2019 11:52 am

I would plus 1 on the previous post and have 2 bits per colour. I think 2 extra pins would be well used on upping the RAM and Flash to 512K Bytes each Nothing to do with me having SST39SF040-70-4C-PHE and AS6C4008-55PCN in stock ;)
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Re: Atom 2k18 ?

Post by roland » Sun Mar 10, 2019 12:23 pm

Good finding Bram. I'll implement that solution. People who think that this is overkill can always place a 125mW resistor in the Source and Drain holes instead of a FET.

I'll think that a 2N7000 or a BS170 (both in TO-92 housing of course :wink: ).


Simon, do you suggest that you actually want such a board as you are already searching for components :lol:
But what on earth should we store in 1MB memory in an Atom? 640 kB ought to be enough :mrgreen:
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Re: Atom 2k18 ?

Post by hoglet » Sun Mar 10, 2019 12:27 pm

roland wrote:
Sun Mar 10, 2019 10:11 am
Interesting proposal! When I only use one 74LVC244 I can connect the keyboard to the databus instead of eight dedicated I/O pins. It requires however one select signal for #B001 so this solution will free seven I/O pins. Hoglet, what are your thoughts about this? Can it free up some resources in the FPGA and what shall we do with the extra free pins?
This seems a good idea, and I don't see any problems.

I think the PS/2 keyboard would then need two dedicated pins.
roland wrote:
Sun Mar 10, 2019 11:30 am
Regarding the mouse interface I have looked at the Godil level shifters, but these are too complicated for my project. I have found another article for a simple interface at https://www.digikey.com/eewiki/pages/vi ... troduction. They only use a few resistors. Any thoughts about that solution?
I would not use that solution with a Spartan 6 FPGA. It's not tolerant of 5V levels, and has no clamping diodes on the input.

I would recommend doing it properly, with a FET based level shifter. It's a few more components, but better to be safe. Also, people do have a habit of plugging/unplugging mice/keyboards into live systems, so this gives the FPGA a bit more protection.

There are lots of solutions here:

Integrated (e.g. the TI TXS range which supports open-drain applications):
http://www.ti.com/lit/ds/symlink/txs0102.pdf
http://www.ti.com/product/TXS0104E
(the TXS0104E is available in a 14-pin SOIC package which is pretty easy to solder)

Or discrete:
https://www.adafruit.com/product/757

Or even more discrete:
http://www.hobbytronics.co.uk/mosfet-vo ... -converter
(Edit: this is the same as Bram's solution)

I would try to prototype it first!

Dave
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Re: Atom 2k18 ?

Post by fordp » Sun Mar 10, 2019 7:13 pm

roland wrote:
Sun Mar 10, 2019 12:23 pm
Simon, do you suggest that you actually want such a board as you are already searching for components :lol:
But what on earth should we store in 1MB memory in an Atom? 640 kB ought to be enough :mrgreen:
You are not thinking laterally. I am good at that. That memory may be a bit of overkill for an Atom. If you load BeebFPGA in there however it is great for sideways ROMs, Sideways Rams, RAM discs an the like.

I will buy a board of course, I really like the sound of this project. I forget to +1 for a raspberry pi connector.
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Re: Atom 2k18 ?

Post by roland » Sun Mar 10, 2019 7:18 pm

Okay, you convinced me. Using another core of this computer is an option - and then having more than 2 x 128k might be nice. Just thinking about some 6809 system running OS/9 or so :)

I'll modify the circuit so that both 128k and 512k memory chips are supported 8)


Edit: I had an 29F010 flash rom in my design because that can run at 3.3V and the 39F010 is a 5V device. It's a bit more mod than I expected.... I have to move the memory behind the level shifters. Will do that in the next days....
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Re: Atom 2k18 ?

Post by fordp » Sun Mar 10, 2019 11:31 pm

Do not be too hasty. The RAM is more important than the flash. This has to be an Atom first with anything else being a lucky bonus I think. I guess if it does not compromise the design 5V memories could be OK. If the address lines are always from the FPGA they may not need level shifting.
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Re: Atom 2k18 ?

Post by hoglet » Mon Mar 11, 2019 8:10 am

I would worry more about SRAM access time.

The BeebFpga core needs fast SRAM (able to run with a cycle time of 32MHz). The AtomFpga core is a bit less demanding (it's 16MHz I think).

If you use a 55ns SRAM the BeebFpga core won't work in it's current form. And it might even be marginal for the AtomFpga core.

The boards I've used so far for these projects are:
- Papilio Duo (8ns SRAM: http://www.issi.com/WW/pdf/61-64WV5128Axx-Bxx.pdf)
- Altera DE1 (10ns SRAM: http://www.issi.com/WW/pdf/61LV25616AL.pdf)

I think the SRAM also need to be 3.3V, to avoid two lots of level shifter delay.

So please give this some careful consideration!

Dave

Here's a few from farnell
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Re: Atom 2k18 ?

Post by roland » Mon Mar 11, 2019 10:05 am

Does the low access time also effect the rom? IMHO there is no difference in reading from a RAM or ROM (from the processor point of view).
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Re: Atom 2k18 ?

Post by fordp » Mon Mar 11, 2019 10:56 am

There is something to be said for not having parallel Flash as it can be much slower than RAM. A common option is to copy the ROM contents from a serial FLASH memory. It may be possible to store the ROMs on the flash chip on the FPGA board?
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Re: Atom 2k18 ?

Post by hoglet » Mon Mar 11, 2019 11:17 am

roland wrote:
Mon Mar 11, 2019 10:05 am
Does the low access time also effect the rom? IMHO there is no difference in reading from a RAM or ROM.
In AtomFpga both RAM and ROM are indeed treated the same. I looked at the various targets I have, and this one uses the slowest SRAM and FLASH (Papilio One plus my own "wing"):
viewtopic.php?p=88030#p88030

The SRAM is 55ns and the FLASH is 70ns. Although the FPGA internal system clock is 16MHz, the fastest "turbo" mode runs the 6502 at 8MHz, which is OK for 70ns ROM.

It's BeebFpga that is more challenging, and the SRAM really needs to run at 32MHz. This is because it's used for the frame buffer, for the Co Processor, and because the original was written in a slightly inefficient way. So in one 6502 cycle a number of different RAM accesses need to be made.

So to summarise, I think we can get away with 70ns FLASH, but if you want to be able to run BeebFPGA it would be best to use ~10ns SRAM.
fordp wrote:
Mon Mar 11, 2019 10:56 am
There is something to be said for not having parallel Flash as it can be much slower than RAM. A common option is to copy the ROM contents from a serial FLASH memory. It may be possible to store the ROMs on the flash chip on the FPGA board?
Ford, yes indeed this is exactly what I do in some targets. A slight digression...

I have a special module called bootstrap that can initialize the external SRAM from the same 8-pin SPI FLASH device that used to configure the FPGA (there is plenty of spare space after the configuration bitstream). I did this to support targets that don't have any parallel FLASH, and so that I would not have to waste FPGA block RAM to implement fixed ROMS.

Here's the AtomFpga version of bootstrap:
https://github.com/hoglet67/AtomFpga/bl ... tstrap.vhd

Only the Olimex MODVGA target currently uses it. This is the Gameduino clone that 8bitguy has been talking about recently. It was the original AtomFpga that AlanD made!

Dave
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Re: Atom 2k18 ?

Post by fordp » Mon Mar 11, 2019 11:27 am

Just to be clear emulating a BBC Master plus 65c02 CoPro would take 128K Master RAM (Equivalent to the 4464 x 4) plus 256K Sideways Space, plus the OS ROMS plus 64K for the Copro. I think that will fit in 512K Bytes, Phew!
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Re: Atom 2k18 ?

Post by hoglet » Mon Mar 11, 2019 12:10 pm

fordp wrote:
Mon Mar 11, 2019 11:27 am
Just to be clear emulating a BBC Master plus 65c02 CoPro would take 128K Master RAM (Equivalent to the 4464 x 4) plus 256K Sideways Space, plus the OS ROMS plus 64K for the Copro. I think that will fit in 512K Bytes, Phew!
Just... you can see the 512KB SRAM layout here:
https://github.com/hoglet67/BeebFpga/bl ... .vhd#L1375

It's laid out with the ROMs first, so the bootstrap code just needs to write from the start.

Dave

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Re: Atom 2k18 ?

Post by roland » Mon Mar 11, 2019 8:27 pm

So ... what do we choose:
  • A 5V Flash rom @ 70ns with level conversion (e.g. SST39SF010A / 020 / 040 )
  • A 3.3V Flash rom @70 ns in a PLCC32 socket (e.g. SST39VF010-70 / 020 / 040, a 55ns version also exists but is hard to get)
  • No flash rom but read 16k (or 32k) from FPGA flash into RAM
We have plenty of RAM so the third option might be a good solution. Although the first two options (in that case I prefer the second one because it's a 3.3V device) do not exclude the possibility to copy contents from the FPGA flash into the RAM.

What are the readers thoughts about this?
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Re: Atom 2k18 ?

Post by hoglet » Mon Mar 11, 2019 10:12 pm

roland wrote:
Mon Mar 11, 2019 8:27 pm
What are the readers thoughts about this?
Definitely the second option seems better to me:
- it's 3.3V so simpler overall
- it's available from Farnell (link) for £0.70.
- you can use a through-hole socket
- it's easier for users to understand how to program it in a programmer
- it's easier to generate a new image than the SPI FLASH option
- it can be reprogrammed in-system (see this post and this post) 4K at a time using the FLASH command in FPGA Utils. This is great fun to do.

Dave
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Re: Atom 2k18 ?

Post by roland » Tue Mar 12, 2019 8:13 am

OK, next point of concern.... what about the VIA and other peripheral that can be connected at the I/O bus like a floppy disk controller?

The 6522 has quite a large access time: 150ns for a 2 MHz device and even 300ns for a 1 MHz device. Will that ever work? I doubt it if we need fast RAM and ROM..... If that is a problem I might consider to get the CPU out of the FPGA (i.e. start all over again with a new design).
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Re: Atom 2k18 ?

Post by 1024MAK » Tue Mar 12, 2019 9:39 am

Yeah, Dave’s post is very persuasive. So a thumbs up 👍 to the second option from me.

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Re: Atom 2k18 ?

Post by 1024MAK » Tue Mar 12, 2019 9:56 am

The modern Western Design Cente CMOS versions are faster and are rated at 14MHz. The W65C22S can run at 3.3V or 5V. When run at 5V, the cycle time is specified as a minimum of 70ns.
Wikipedia entry on the WDC 65C22 here
65C22 page on WDC site
Datasheet here
They are available from some of the larger electronic suppliers.

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Re: Atom 2k18 ?

Post by 1024MAK » Tue Mar 12, 2019 10:08 am

For slow 1MHz I/O devices, if there were enough FPGA pins, I would suggest a separate “slow” bus. Writes to a slow bus device could be latched in a buffer and it’s outputs held until the external device had had enough time to capture the data. Alternatively a CPLD could be used to do the same thing using data from the normal “fast” data bus.

For reads, from the external device, the CPU would have to be paused if running too fast until until the device had enough time to respond.

A read immediately after a write could be a problem though.

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Re: Atom 2k18 ?

Post by hoglet » Tue Mar 12, 2019 11:35 am

roland wrote:
Tue Mar 12, 2019 8:13 am
The 6522 has quite a large access time: 150ns for a 2 MHz device and even 300ns for a 1 MHz device. Will that ever work? I doubt it if we need fast RAM and ROM..... If that is a problem I might consider to get the CPU out of the FPGA (i.e. start all over again with a new design).
First, let's think about the Atom, as that's the primary target.

Although the internal system clock is 16MHz, a clock enable signal is used on the 6502 core so it is only actually clocked 1 in N cycles:
- N=16 gives a 1MHz Atom
- N=8 gives a 2MHz Atom
- N=4 gives a 4MHz Atom
- N=2 gives an 8MHz Atom

The address and control signals that the 6502 outputs stay stable until the next clock enable. So in effect, it is being clocked slowly.

(It's done this way because it's easier to design reliable FPGAs if everything runs off a single global clock, without any nasties like clock gating or stretching, etc. It's also what all the design tools need to be able to perform an accurate timing analysis.)

Now, the Atom only needs fast RAM/ROM to support running at 8MHz (same as a real Atom would). At 2MHz, there is approximately 500ns where the external address bus is stable, so it should be possible to connect a real 6522 and make this work. We just need to generate appropriately timed external Phi clock (which is not currently done but would be easy to add).

So I think it's no problem to run with a real 6522 externally, or in fact run with any original Atom device connected to the PL6/7.

Now, in 8MHz mode if the external bus ran at 8MHz then much not would actually work reliably, but that's no worse than a real Atom. In fact, it's still better: the 8255 is internal, so the system will be stable and usable. Only the 6522 might not work reliable.

One solution would be to use a faster 6522, e.g. a W65C22 which can run at 14MHz. Another approach would be to design some logic to add wait state(s) where accessing slow external devices. That's part of the fun of this approach. You can start simple and incrementally make improvements / add new features without have to design a new PCB each time. I think you would loose that if you switched to plan B with a real 6502.

Now In terms of the Beeb, I don't think it would be possible to share the external bus between the SRAM and the 6522, as the SRAM is active all the time. So I think that limits you to using BeebFpga as it currently is, with both 6522s internal, and any external 6522 disabled. I don't see a problem with that.

Edit: And I think plan B would preclude the Beeb use case entirely.

Dave
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Re: Atom 2k18 ?

Post by roland » Tue Mar 12, 2019 12:31 pm

Thanks Dave for your explanation. If the problems only arise at CPU speeds above 2 MHz then I can live with that. Currently my Atom can run at 4 MHz and the VIA and disc drive don't work then. In real life, those higher clock speeds are not often used because many games have counter or loop based timing and run too fast > 1MHz.

I'll update my diagram and post the first draft soon.

BTW ... where can I buy SOJ-32 to 32 pin DIP sockets for a reasonable price?
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Re: Atom 2k18 ?

Post by fordp » Tue Mar 12, 2019 12:46 pm

Did you mean PLCC32???

For PLCC I guess China is the answer:

e.g.
https://www.aliexpress.com/item/Complet ... st=ae803_4
These may not be exactly what you are looking for.
Or maybe this: https://www.aliexpress.com/item/14-pcs- ... d911a49-24
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Re: Atom 2k18 ?

Post by hoglet » Tue Mar 12, 2019 12:51 pm

roland wrote:
Tue Mar 12, 2019 12:31 pm
BTW ... where can I buy SOJ-32 to 32 pin DIP sockets for a reasonable price?
Do you mean SOJ-36 for the SRAM?

Or you mean PLCC-32 for the FLASH?

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