I'm not an Altera expert either!adrm wrote: So, what is the approved way to resolve this?
E.g. feed CLOCK_50 into multiple SIGNALS and then feed these into the PLLs?
But, this does seem to be a rather nasty / fundamental limitation of Cyclone II:
And it's why the DE1 feeds the same clock in on multiple pins. Shame they forgot this trick on the DE2!
It's worth googling the exact error message, just to see if there is an easy answer, but I suspect not.
I can think of a few ways to work around this (in order of difficulty):
1. Use one PLL to go from 50MHz to 32MHz and a second PLL to go from 27MHz to 24MHz (and drop the second scan doubler).
2. Use one PLL to go from 50MHz to 96MHz, then a /3 counter to get 32MHz and a /4 counter to get 24MHz.
3. Use a fast counter to generate a 24 and 32MHz clocks that are not quite regular, but have the right average frequency. See here for an example. This is quite hard to get your head around, so I'd try the others first.
You are getting a bit of a baptism of fire here!