So, I developed the previous circuit further, making the counter readable via &FC80. This requires some multiplexers (74HC4052) so that the outputs from the counters (Q0..Q3 from each 74HC193) are isolated from the data bus until the appropriate selection condition is present, whereupon the multiplexer channel is enabled. In fact, I just use one channel in the multiplexers, setting E# (output enable negated) low when the CPU wants to read from &FC80.
For eight data bits, I need four 74HC4052s, so this boosts the chip count to thirteen! (One 74HC04 for the reset handling, six 74HC193s for the counter, two 74HC138s for the address selection logic, and four 74HC4052s for the output multiplexing.)
- Cartridge with readable and writeable counter
It's now possible to do something like this:
Code: Select all
?&FC80=100:REPEAT:PRINT ?&FC80:UNTIL FALSE
This sets the counter and shows it counting down. The rate is still leisurely - each unit is sixteen bits' worth of cycles - but the aim would be to make the counter a multiple of, say, four bits' worth of cycles (sixteen), which is arguably the minimum sensible unit for what I envisage this being useful for. In fact, I happen to have a 14-bit binary counter IC (74HC4060), which might be worth trying, and then I'd almost be back to using one breadboard again.
However, one thing I want to investigate is setting an interrupt condition (IRQ#) when the counter crosses zero. This might need another multiplexer to isolate the signal from the bus until I actually want to hold IRQ# low. The 6502 isn't so sophisticated with regard to interrupts, and the ULA doesn't seem to provide additional assistance, so to know whether it is my interrupt being signalled, I'm supposing that the counter is the mechanism that a handler uses to test whether the interrupt just happened, as opposed to something like the VSYNC interrupt.
