Converting ABR and ATI for EEPROM (28C256)

[daveejhitchins]

You MUST follow these instructions very carefully - Electron ONLY!

(1) Remove the Battery

(2) Remove the RAM

(3) Fit AT28C256

(4) Enjoy

Dave H

[danielj]

[dixiestoat]

Blimey.
Even I can manage that.

[CMcDougall]

was actually thinking of that yesterday! While playing Elite CoPro on the Electron & plus1...

still waiting for my 5x chips for £4 from China, then can do it

[MartinB]

still waiting for my 5x chips for £4 from China, then can do it

Mine arrived safely last week (ordered when I said I would try them on whichever thread it was) and were all good...

[daveejhitchins]

I've carried out some more testing:

Point #1: This ONLY works for the Electron! However, On my Master, same as the MGC, it works for a short while then stops working. MUST get to the bottom of this issue - Currently: House in the process of being internally changed - Workshop too full to do any 'serious' work. So this may have to wait a while.

Point #2: Even on the Electron - if you remove the DS1210 and link pins 5 & 6 (nOE in/out) it doesn't work!!! Double investigation needed.

If anyone has any ideas, I would be very grateful to hear them . . .

Note: I've marked the first entry with "Electron ONLY".

Dave H

[Prime]

Could this be a problem with the write cycle not being finished?

I know in my writer code for DragonMMC which will also use a 28c256, that certainly the Atmel ones can be written in pages of 64 bytes. But at the end of each page you have to poll the EEPROM to find out if it has finished writing yet.

Cheers.

Phill.

[daveejhitchins]

@Phill . . . No, Not really! The MGC, ATI and ABR all have their write signals inhibited at power-up. I have been stumped with the MGC, however, now the ABR does the same - The only difference with the ABR is the EEPROM, so I think I'll be looking at access times - maybe it not working with the DS1210 removed is a clue. At least I thought so. The delay of the nOE, through the DS1210 is a maximum of 20ns . . . I tried to replicate this with a series resistor, but I may need to add a proper RC delay to ensure accuracy . . . BUT, 20ns !!! If I can solve the DS1210 issue maybe it'll be a pointer to what's happening?

Dave H

[danielj]

I just stuck an eeprom in my Care electronics cartridge in my master, and it corrupted it - twice. Is that to be expected?

d.

[CMcDougall]

^yes, if you try loading in any ADFS
was there not a link in the Master128 for cartridges to act different, DaveH done it to mine, then his MGC worked on mine, not sure which one it was though....

[daveejhitchins]

@Col . . . All that particular link does is ground a pin on the ABR etc. to swap the R/nW line from the Elk to the Master pin in the Cartridge. Link 12 IIRC.

Dave H

[1024MAK]

I just stuck an eeprom in my Care electronics cartridge in my master, and it corrupted it - twice. Is that to be expected?

d.

I *think* Martin may have talked about similar issues in his E2PROM / EEPROM thread when talking about Acorn EPROM/ROM carts.

A link may be available tomorrow (if/when I find it )

Mark

[MartinB]

I don't think I've ever had any corruptions issues as such, but you can get a hang on <Break> without a Write Protect switch. Masters remain an enigma, I didn't get even the basic E2 in a rom socket working - on my to do list.
Anyway, to save you looking Mark, here's the link to my thread about the mods needed to configure E2 in a cartridge.

It's surprisingly short for me too....

[danielj]

Odd, it was absolutely fine (testing upurs), then tried an upxssd and bang! Everything hung beeping away. Checked the eeprom in my programmer and it was corrupted. Reprogrammed, back in the master and corrupt again (from the off this time), despite it having verified fine in the programmer.

I'll just save those for the elk/beeb... (it was a 28C256).

d.

[daveejhitchins]

Hmmm! I think it's prize giving time . . . For anyone who can suggest/find the answer to the Master 28C256 problem.

Looking at the data sheet seems to suggest that all should be well! IIRC when I was looking at the MGC, in a Master, I used one of the PLDs to remove, in turn, each of: nOE, nCE, R/nW (which was effectively disconnected anyway). The only one that allowed the MGC to stay in the cartridge slot was nOE being disconnected . . . So that may be starting point?

Big problem with MGC is the fact, in my Master, it totally hangs the machine* - to the point of ctrl-brk has no effect. So you can't even look at the signals. The ABR/ATI behave a little differently - they just disappear from a *ROMS list. So I should be able to still 'see' what's going on. Maybe?

* This occurs after about 30s of being OK - Maybe some freezer spray may help in finding the culprit?

Dave H

[paulv]

From a pure software engineering viewpoint the differences between elk and master you've described and the resulting symptoms in the master sound to me like it's a pure software issue in the programming of the logic you have on board.

The Elk and Master already have different routes in the software so if there's something being set in the Elk route that is not being set in the Master route that is later depended on that could cause all sorts of issues.

As it takes 30 seconds to occur on the master it's likely to be a cumulative issue.

I'd re-examine any code that handles interrupts to see it things are either getting out of sync to the point where the machine enters a deadly embrace where the signals are in such a state as to be impossible in normal running but happen after time with the cart fitted.

Paul

[MartinB]

Either that or it's buggered....

[daveejhitchins]

@Paul

From a pure software engineering viewpoint the differences between elk and master you've described and the resulting symptoms in the master sound to me like it's a pure software issue in the programming of the logic you have on board.
Not so sure!

The Elk and Master already have different routes in the software so if there's something being set in the Elk route that is not being set in the Master route that is later depended on that could cause all sorts of issues.
The only difference, in the hardware, is the routing of the R/nW line. The ABR, with RAM fitted, works OK. Just replacing the RAM for EEPROM (leaving the battery in place or removed) works in the Electron but not in the Master (caveat: works in my Master for a short time - Could someone else check in a Master, please). So I believe the problem is related to the 28C256 and it's required timing. I've been browsing the datasheet: The only thing I've noticed is the different edge-to-data-valid, on a read: TCE=150ns : TOE=75ns. At the moment, I'm not sure if this has any significance? But, maybe it does - as removing the DS1210 kills the ABR/ATI in an Electron too (but doesn't hang the machine!) - that's just removing an up-to-20ns delay for nCE! I really do need to look at just what is going on here . . .


As it takes 30 seconds to occur on the master it's likely to be a cumulative issue.
This is a MGC and only on my Master . . . At the last Halifax meeting I tried several Masters - all wouldn't boot at power-up e.g. totally hung! ABR/ATI just stop being 'visible' - no hangs. The MGC uses 'similar' R/nW control (external on MGC - Internal [PLD] on ABR/ATI) but different write protect - MGC data latch controlled - ABR/ATI Address latch controlled.
I'd re-examine any code that handles interrupts to see it things are either getting out of sync to the point where the machine enters a deadly embrace where the signals are in such a state as to be impossible in normal running but happen after time with the cart fitted.

Dave H

[daveejhitchins]

Some testing carried out:

Top trace is nCE (trigger), bottom trace nOE : With the DS1210 fitted. nCE is delayed by around 8ns.

Top trace nCE (trigger), bottom trace nOE : No DS1210 fitted. Coincident?

I've tried to replicate to nCE delay, of around 8ns, using a resistor and the gate input capacitance (around 7pF) and failed! The result of removing the DS1210 is: No data out on a read!

Tomorrow, I'll try adding a standard non-inverting buffer and see what that produces. I can add a delay, to the front of it, with a variable R, and see what happens.

Dave H

[Prime]

Another random thought....You're not getting glitches on the /WE line are you?

I'm presuming that you are generating /OE and /WE from the R/W and phi2 signals (in one of the PALS).

What speed / make of 28C256 are you using?

Cheers.

Phill.

[daveejhitchins]

@Phill . . . Another random thought....You're not getting glitches on the /WE line are you?
I haven't seen any. Write is inhibited completely by the PLD - see below.

I'm presuming that you are generating /OE and /WE from the R/W and phi2 signals (in one of the PALS).
Yes, nOE = !nW

What speed / make of 28C256 are you using?
AT28C256 -15

Code: Select all

Name     ABR-Issue1-30-05-13 ;
PartNo   16L8 ;
Date     01-06-13 ;
Revision 01 ;
Designer D.E.J.Hitchins ;
Company  Retro Hardware ;
Assembly Advanced Battery Backed RAM ;
Location IC3 ;
Device  g16v8ma ;

/* *************** INPUT PINS *********************/
PIN 1   =  NOE                    ; /* Not-Output Enable               */ 
PIN 2   =  ERNW                   ; /* Electron Write  */ 
PIN 3   =  QA                     ; /* Page latch LSB - 16A EC         */ 
PIN 4   =  A1                     ; /* Address line 1 - 17B EC         */ 
PIN 5   =  A0                     ; /* Address line 0 - 18B EC         */ 
PIN 6   =  T2                     ; /* CPU clock phase 2               */ 
PIN 7   =  A5                     ; /* Address line 5 - 13B EC         */ 
PIN 8   =  MADET                  ; /* Master detect Low if Master     */ 
PIN 9   =  MRNW                   ; /* Master Write                    */ 
PIN 11  =  NA23467                ; /* N&'ed add. lines 2,3,4,6&7      */ 
PIN 15  =  NPFC                   ; /* Not-Page &FC - 14A EC           */ 

/* *************** OUTPUT PINS *********************/
PIN 12  =  !NCS                   ; /* Not-Chip Select                 */ 
PIN 13  =  !NRNW                  ; /* Not-Output Enable on Read Only  */ 
PIN 14  =  !BIN                   ; /* Chip 'B' inhibit latch          */ 
PIN 16  =  !BEN                   ; /* Chip 'B' enable latch           */ 
PIN 17  =  !AIN                   ; /* Chip 'A' inhibit latch          */ 
PIN 18  =  !AEN                   ; /* Chip 'A' enable latch           */ 
PIN 19  =  !RNW                   ; /* Low output Read Not-Write       */ 

/* *************** LOGIC EQUATIONS  ****************/

NCS =    NPFC & !NOE &  NRNW & T2 & ERNW				/* CS on Read 	*/
	# NPFC & !NOE & !NRNW & T2 & !QA & AEN & !MADET
	# NPFC & !NOE & !NRNW & T2 &  QA & BEN & !MADET 
	# NPFC & !NOE & !NRNW & T2 & !QA & AEN &  MADET
	# NPFC & !NOE & !NRNW & T2 &  QA & BEN &  MADET;

AEN =	   T2 & !NRNW & !NPFC & !A0 & !A1 & !A5 & !NA23467	/* Unlock  &FCDC */
	# !AIN;

AIN =	   T2 & !NRNW & !NPFC &  A0 & !A1 & !A5 & !NA23467	/* Lock  &FCDD	*/
	# !AEN;

BEN =	   T2 & !NRNW & !NPFC & !A0 &  A1 & !A5 & !NA23467	/* Unlock &FCDE */
	# !BIN;

BIN =	   T2 & !NRNW & !NPFC &  A0 &  A1 & !A5 & !NA23467	/* Lock &DCDF */
	# !BEN;

RNW =	  !MADET & !MRNW & T2 & !QA & T2 & AEN			/* Write  */
	# !MADET & !MRNW & T2 &  QA & T2 & BEN
	#  MADET & !ERNW & T2 & !QA & T2 & AEN
	#  MADET & !ERNW & T2 &  QA & T2 & BEN;


NRNW =   !MADET & MRNW			/*  Select Write	*/
	#  MADET & ERNW;				/*  Master or Electron */

I'm aiming to remove T2 from nOE (NRNW) - This should then allow nOE to be asserted earlier e.g. increasing the 'gap' between NOE and nCE - I then may have enough 'space' to remove the DS1210 and still have nCE active after nOE.

Dave H

[daveejhitchins]

I finally have an answer to why the 28C256 doesn't work when I remove the DS1210 . . . And I don't understand it!

Today I've spent time looking at the PLD equations. They came from the original ABR, so no real changes. I've tidied them up, a little, reducing a particular through-put time - It hasn't made a jot of difference to the problem I've been looking at, however, it refreshed my thoughts on the the way it all works. Nothing I have done, in the PLD makes any difference whatsoever.

The first hardware testing consisted of replicating the problem e.g. Just remove the battery from the ABR then replace the RAM with EEPROM. Works OK. Remove DS1210 and fit a link between pins 5 & 6. Stops working.

Thinking about the delay, I noticed yesterday, I used a single gate, from a 74LS32, as a delay element (around 12ns). Still didn't work! Tried 2 gates in series. Still didn't work.

Took some photos with and without the DS1210 . . . Spot the difference - remembering that I'm sure the delays are a red-herring!
Clue: You need to look at the top trace.

No DS1210

With DS1210

Well that was easy(?) The only difference is the level 4V peak to 5V peak To confirm this actually was the problem - I used a gate from a 74HCT08 as a buffer. Worked . . . .

The same 28C256 works OK in the AP6 which has a 4V peak nCE drive - At this point I scream . . . ANYBODY got any ideas?

Dave H :

[CMcDougall]

got my 5x Amtel EEPROMS today for £3.28, so gave 3 a spin on my ATI.
they all have the same date stamp on them, but are different chips (writting on bottom), and one does not have anything written on it
anyways, seems not to be playing ball with mine

i did not try them in the eUPURS board, as it's a bit fiddly with the 2 jumpers on top right.
Dave, just wanted to confirm what prog you are using to load into the swram, as i'am using MartinB's EEPROM utils
and this works fine, again, when I put the battery back in and the Alliance 32k chip.....

[1024MAK]

got my 5x Amtel EEPROMS today for £3.28, so gave 3 a spin on my ATI.
they all have the same date stamp on them, but are different chips (writting on bottom), and one does not have anything written on it
anyways, seems not to be playing ball with mine

i did not try them in the eUPURS board, as it's a bit fiddly with the 2 jumpers on top right.
Dave, just wanted to confirm what prog you are using to load into the swram, as i'am using MartinB's EEPROM utils
and this works fine, again, when I put the battery back in and the Alliance 32k chip.....

That does not sound good
Brand new 28C256 are suppose to be supplied unlocked. If what you have are fake chips or used "pulls", this will not be the first time that some have been found. From what this poster says in this thread and in this thread, it sounds like she ended up with either fake chips or used "pulls"

Mark

[CMcDougall]

^

Mine arrived safely last week, and were all good

Mr B must of been lucky, and I maybe got the 'bag of sh!t#' as per

[MartinB]

Lucky is my middle name Col

I did a quick check on all 5 and they seemed to be fine but in view of your findings I'll try something a bit more thorough over the weekend......

[daveejhitchins]

@Col . . . Not tried them in an ATI, as yet. And, due to family visits, unlikely to get into the workshop any time soon. I'll try, though and let you know.

I'm using the AP6 ROM for loading to EEPROM, however, MartinB's utilities should work fine as I use that too. A suitable ROM, for your Plus 1, is available on the first post of the AP6 thread. It's the 8K version you need.

Dave H

[duikkie]

Always troubles with search . Search for ap6 rom on this forum not possible. Link ? 8k plus1.

[1024MAK]

In a Google search box type "site:http://stardot.org.uk/forums/ AP6" and you will find

Mark

[dv8]

Colin,

The command to unlock the EEPROM should be

EEP32 UNLOCK 23