Variable phi2 frequency.

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Prime
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Variable phi2 frequency.

Post by Prime » Tue Jan 30, 2018 4:55 pm

Hi all,

Some of you will have no-doubt seen my System clone at the recent meetup, I'm now thinking about enhancements.....

So I can get a WD65C02 CPU that is rated for 14MHz, whilst I don't think that it will be possible to run the whole system at that speed I would think 4-6MHz should be possible. One sticking point however is the 6845, which is only rated at 1MHz, it won't even work at 2MHz, just fails to initialize.

So I was thinking of some address dependent clocking for phi2, so that most access could happen at whatever clock speed I'm running at and drop back down to 1MHz for 'slow' things like the 6845 & 6522.

The way I currently have this implemented is I have a master clock of 24MHz, that drives a count down register, which is loaded on the rising edge of phi2, in such a way that if a 'slow' address is detected a longer count is loaded (the phi high to low happens when the count is halfway down). This way you should get no glitch in clock speed switching and it certainly seems to work.

Can anyone see any disadvantages in this method?

One potential pitfall is that IIRC timers in the VIA are based off the phi frequency are they not?

I'll post the verilog code I'm using to do the switching later :)

Cheers.

Phill.

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roland
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Re: Variable phi2 frequency.

Post by roland » Tue Jan 30, 2018 9:53 pm

Prime wrote:
One potential pitfall is that IIRC timers in the VIA are based off the phi frequency are they not?

That is correct. Various timers, counters and the shift register use phi2 as the time base.
256K + 6502 Inside
MAN WOMAN :shock:

crj
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Re: Variable phi2 frequency.

Post by crj » Tue Jan 30, 2018 11:47 pm

Prime wrote:One potential pitfall is that IIRC timers in the VIA are based off the phi frequency are they not?
Depending on how you implement things, that needn't be a major obstacle.

Instead of stretching the 24MHz clock to 2MHz for "slow" accesses, you could keep synchronous 24MHz and 2MHz clocks running, and transition between the two as needed. The downside is that you'd have to wait an average of an extra 250ns for each 2MHz access, but the upside is you'd avoid problems with chips that had to be continuously clocked.

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