A bit more progress to report....
I've now got the multi boot firmware working: a boot loader design reads the ID and Mode links on the adapter board, and loads one of the following designs:
- ICE 65C02
- ICE Z80
- Unknown adapter
All of these are packaged into a single firmware image, so there is no need to keep reprogramming the FPGA board.
At the moment fitting only R10 (ID0) indicates a 6502/65C02 adapter, and fitting only R11 (ID1) indicates a Z80 adapter.
I've also been doing some more work on the 6502 variant. There are now seperate ICE-6502 and ICE-65C02 builds, and the boot loader selects between them based on the Mode jumper. ICE-6502 uses the T65 core and ICE-65C02 uses the AlanD core.
I've added support for Rdy on both flavours, which was quite interesting (thanks to BigEd for his help yesterday).
Testing on the Beeb showed the first a problem. The system booted but then immediately froze, and not even BREAK would work. It turns out on the Beeb, the Rdy input (pin 2) of the 6502 is basical just left floating. I'm actually surprised this has not been noted before. It's certainly bad practice, and might be an additional source of unreliability when 65C02 processors are fitted.
Anyway, to get it working I added a weak pullup to the bottom of the level shifter, between pins 2 and 8:
(I could have fitted this to the Beeb instead, as technically it's the Beeb that's at fault)
But based on this experience, I've reved the PCB to add weak pullups on all of the optional 6502 control inputs (R15-R20):
I'll order some more 6502 boards shortly when I send off the 6809E design.
Testing on the Acorn External 65C02 Second Processor was also interesting:
Two aspects of the External 65C02 Second Processor design are unusual; both relate to DRAM refresh:
- To make time for DRAM refresh cycles, the 65C02 is paused (using Rdy) for one cycle 3MHz cycle every ~14us. So effectively the 65C02 is only running at 2.93MHz, rather than 3MHz. Not something Acorn ever advertised! I've often wondered why ClockSP didn't show exactly 3MHz.
- DRAM refresh is triggered by the Sync signal (along with a counter). So when the ICE was paused, after about 10 seconds DRAM would become corrupted. The fix for this was the same as for the Z80 - adding a small state machine to generate Sync cycles when paused (as if NOP was executing).
With these fixes in place, ICE-65C02 runs perfectly and I've been able to play Tube Elite in slow motion using the single stepping feature!
Next up will be finishing the 6809E design.