Matchbox sized 6502 / Z80 / 6809 Co Pro

discussion of games, software, hardware & emulators relating to the Acorn Atom and Acorn System machines.
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hoglet
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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Mon Feb 09, 2015 8:53 pm

JGH,

Another great suggestion (which is why I love this forum!!!)

The code has some self-checksumming, but I managed to disable it by NOPing out the conditional jump at 1000:3e6d

Code: Select all

1000:3e62 3307                 xor    ax, [bx]
1000:3e64 d1c0                 rol    ax, 1h
1000:3e66 83c302               add    bx, 02h
1000:3e69 e2f7                 loop   3e62h
1000:3e6b 0ac4                 or     al, ah
1000:3e6d 75b6                 jnz    3e25h
1000:3e6f ba2b3f               mov    dx, 3f2bh
The place where it goes off into the weeds is the call all 1000:4e58

Code: Select all

1000:4e54 loc_00004e54:
1000:4e54 b002                 mov    al, 02h
1000:4e56 b202                 mov    dl, 02h
1000:4e58 ff1e0c03             call   [30ch]
If you look at the contents of [30ch] it is 1689:4be8 which is valid.

Code: Select all

1000:4be8 87da                 xchg   dx, bx
1000:4bea e83d02               call   loc_00004e2a
1000:4bed cd4b                 int    4bh
1000:4bef e84d02               call   loc_00004e3f
1000:4bf2 87da                 xchg   dx, bx
1000:4bf4 cb                   retf
Now, working through this, all instructions are executed, but then RETF jumps into the weeds. So something is messing up the stack.

Moving the RETF back through the code, it looks like it is the INT 4B, which I think is an OSBYTE: AL=02 BL=02 BH=00 which is *FX 2,2

Now, what's very interesting is that as I move an illegal instruction through this block of code, and look at the value of SP in the dump:
4BE8 : SP=02F0
4BEA : SP=02F0
4BED : SP=02F0
4BEF : SP=02EE
4BF2 : SP=02EE
4BF4 : SP=02EE

So it looks like the bug is that the INT 4B is swallowing two bytes of stack.

By the way, all of this debugging is being done with EDBIN.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by firthmj » Mon Feb 09, 2015 9:17 pm

jgharston wrote:
firthmj wrote:I think JGH has already proposed a DIP switch address reshuffle - I guess that may be looked at if it is decided that the original 4MHz external RAM 6502 Co-Pro is obsolete.
I certainly remember the ROM type bytes more easily than the current DIP settings - and it would be useful if we ever got the ability for the host computer to tell the matchbox what CPU to run, then the host can select the right CPU for the code it wants it to run by just writing the ROM type byte to it.

Is the CoPro speed hardwired into the specific CPU implementation - could it not be selectable independently of the CPU selected?

Three of the Tube status registers are read-only, so they could be used to write control information to - I'd recommend only using the bottom 6 bits to match Status1. For example, for example, LDA #ROMTYPE:STA &FEE6 could over-ride the DIP switches until the next power cycle(*), LDA #SPEED:STA &FEE4 could specify clock speed.

(*)Programatically, you'd have to put the matchbox CPU in the reset state by setting the RST bit in the control register at &FEE0, the change the CPU, whereupon the new CPU would be held in the reset state, then release the reset state to allow the CPU to start up.

Though, while typing this, it occurs to me - could the "deselected" CPU just hibernate until it is reselected? I admit I haven't delved too deeply into the hardware implementation of the matchbox.
At the moment (and likely to stay that way for space reasons) each CPU is a different FPGA image, and there is a "boot image" that looks at the DIP switches, and then reloads the FPGA with the selected "main" image.

It would probably be possible to put the reloading logic into the main images, so that it was possible to reload under program control in a way similar to what you are saying, but as this is really Dave/Jason's baby, I'll leave it to them as to whether this is something that they want to pursue - it certainly would be quite a major code change.

One advantage of the current layout is that the only image that knows about what images exist, and where they live in the flash is the "boot image". This means that if the image mapping changes, or more images are added, then in theory only the boot images and the MCS packing needs to be redone.
That said, I tend to do a "burn and rebuild" of everything when making an MCS - it makes it much more certain what is in the build.

The CPU speed is also "local" to each FPGA image - there is a 32MHz oscillator on the board that is multiplied / divided as needed in the FPGA logic to create the clock(s) needed for each mode.

I did think about adding soft speed selection, and certainly speed read back, to the design I've been tinkering with, but haven't progressed this yet. One challenge is that there would probably need to be some sort of check pattern, to prevent code that was written for the standard Co-Pro accidentally changing the speed with a spurious write to &FEE4. It would also be useful to have a readable check pattern, so that code could know it was in the LX9 CoPro, rather than any other kind.

Hopefully this will have helped!

Regards

Michael
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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Mon Feb 09, 2015 10:28 pm

I think I understand what's going on now...

All of the DOSPLUS MOS INTs (&40-&4F) are borked. These are the ones implemented by the code in the Client ROM in the Co Pro.

If I write some simple BBC Basic assembler:

Code: Select all

MOV AX, &41
INT &49
RETF
Then this crashes big time. Same code works fine on the emulator.

Here's the cause of the problem. The client ROM exists at segment F000 and is copied to segment 0000 on boot. On the Co Pro, the MOS INT vectors are pointing to the copy in segment 0000. However, I believe this code is long gone having been over-written by DOSPLUS.

On an emulator, they all point to the ROM copy in segment F000, not the RAM copy in segment 0000.

Why the difference?

I think it's down to the client ROM doing different things for the 186 and 286 hardware:
PUSH SP
POP AX ; Push SP and pop it to AX
CMP AX,SP
JNZ L0A30 ; If popped value different, running on 80186
;
; The 80186 changes the value of SP before saving it, so pushes to the stack
; the value that SP has after the push. The 80286, on the other hand, saves
; the value that SP had before the operation started. Consequently, if the
; popped value is different, the code is running on an 80186.
;
; If a non-80186 is found, make Tube INT vectors and (C) address point to RAM
; copy of ROM by changing vector segment from &F000 to &0000. (Why?)
;
Maybe the older Acorn 80286 hardware (which pre-dated the 80186) removed the ROM from the memory map (like the other 8 bit Co Pros do)? Who knows...

Anyway, so I'm thinking there is an easy fix. A one byte change in the Client ROM to change the above JNZ to JMP.

Only it doesn't work.

It seems to break all tube data transfers.

I think this is because the 286 hardware (and the LX9 Co Pro) uses NMI for data transfers, and the code is self modifying, and so this won't work in ROM.

To be continued...... :lol: :lol: :lol:

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Mon Feb 09, 2015 11:01 pm

Finally got it working.

This time with a two-byte change to the client ROM, that leaves the MOS INT vectors pointing to ROM, but the hardware interrupt vector pointing into RAM. That was enough to allow the data transfer routines to load the boot loader.

Code: Select all

PUSH DS
SUB  AX,AX              ; AX=0
MOV  DS,AX              ; DS=0
MOV  BX,0033h           ; BX=>INT &0C vector segment high byte
MOV  [BX],AL            ; Make INT &0C vector to RAM copy at 0000:1FD6
MOV  BX,05B7h           ; BX=>segment high byte of address of &00,"(C)" string
MOV  [BX],AL            ; Change address to be to RAM copy at 0000:1DA8
MOV  BX,0103h           ; BX=>segment high byte of INT &40 vector
MOV  CX,0010h           ; 16 vectors to change
L0A28:
MOV  [BX],AL            ; Make vector segment point to RAM copy at &0000:xxxx
ADD  BX,04h             ; Step to next vector
LOOP L0A28              ; Loop for all 16 vectors
POP DS
The fix was to NOP out the MOV instruction at L0A28.

And with this, the JHG (I think) version of BBC Basic will now boot.
IMG_0813.JPG
At the moment I'm not aware of any further bugs to track down.

Latest code in github....

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by TheCorfiot » Mon Feb 09, 2015 11:57 pm

firthmj wrote:
TheCorfiot wrote:@firthmj

Thanks so much for your build, much appreciated.
Would it be possible for you guys to add a switch description diagram along with your updated mcs files please so it is clear what the dip switch settings actually select.

Many thanks to you all
:)
I did realise after posting that I should probably have detailed this!

The settings for mine are the same as previously:

1 2 3 4
0 0 0 0 65C02 (Original 4MHz using external RAM)
0 0 0 1 Z80
0 0 1 0 6809
0 0 1 1 x86
0 1 0 0 BIST

Plus the following 4 new options:

1 2 3 4
1 0 0 0 65C02 Internal RAM, 32MHz
1 0 0 1 65C02 Internal RAM, 16MHz
1 0 1 0 65C02 Internal RAM, 8MHz
1 0 1 1 65C02 Internal RAM, 4MHz

If you can access the DIP switches while the board is plugged in (i.e. if you have an extension cable) then for the "DIP switch 1 set" design you can change DIP switches 3 and 4 on the fly to change the clock speed. Any other DIP switch changes require a power cycle to reload the firmware.

I think JGH has already proposed a DIP switch address reshuffle - I guess that may be looked at if it is decided that the original 4MHz external RAM 6502 Co-Pro is obsolete.

Regards

Michael

Hi guys

Sorry to be a pest.
I have just reflashed a copro and find that the DIP switch settings do not co-relate to the listing above at all.

I don't know if it's me but I think we are reading the DIP switch incorrectly, I have double checked this with a Meter and with the connector pointing downwards the DIP switch settings are Left=Off or 0 and Right=On or 1

So the original 65c02 should list 1 1 1 1
But the startup banner reads Acorn 6502 Tube, setting to 0111 then you are greeted with 65C102...Something seems to have gotten mixed up.

Can someone please double check.

Thx
:)

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Tue Feb 10, 2015 8:02 am

hoglet wrote:At the moment I'm not aware of any further bugs to track down.
Of course, we all know what happens when you say that out loud :lol:

The D86 debugger is still hanging on start up - and this is working in the emulator. D86 would be really nice to have working, as it would make any future debugging much easier.
TheCorfiot wrote: Can someone please double check?
Is it possible that some of the DIP switches are mounted upside down?

Mine has "On" written on the side farthest away from the Xilinx chip.

But remember, "On" actually means "0" not "1", as it is shorting the input to ground.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by danielj » Tue Feb 10, 2015 8:12 am

Great work Dave! You're a debugging machine. =D>

The only other thing was the two byte transfers (Econet special case)... Unless you've got that sussed? No pressure, mind :D (I'm happy to do some testing around this as soon as I've got my programmer here).


d.

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by TheCorfiot » Tue Feb 10, 2015 8:14 am

Hi Dave

Thanks for knocking some sense into my brain lol.
Ok, that explains the 0 or 1 state, so 0 0 0 0 is supposed to be the original 65c102 ext Ram core.

Problem is that is not what appears on the screen, I get the Acorn 6502 banner, and the different speed cores dont seem to be accessible....Help

:)

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Tue Feb 10, 2015 8:18 am

danielj wrote:The only other thing was the two byte transfers (Econet special case)... Unless you've got that sussed? No pressure, mind :D (I'm happy to do some testing around this as soon as I've got my programmer here).
I'd conveniently forgotten about this one as well.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by jgharston » Tue Feb 10, 2015 12:11 pm

hoglet wrote:Finally got it working.
This time with a two-byte change to the client ROM, that leaves the MOS INT vectors pointing to ROM, but the hardware interrupt vector pointing into RAM. That was enough to allow the data transfer routines to load the boot loader.
Hurray! I'll add that to the Client Bugfix Patch.

I think it's likely that only 80186 CoPros existed when Richard Russell was testing M512 BBC BASIC, so the bugs in the CoPro client's 80286 operating mode would not have come to the surface. Going through the code, I can't see any reason for pointing the INTs to the RAM copy of the Tube Client, especially as as soon as anything gets booted it get overwritten. And if it was for a putative full-1024K RAM version, then why not copy it underneath itself at the top of memory, as other CoPros do? All 16-bit 80x86 environments reserve the top of memory for the host interface code, so that's where it should be.
firthmj wrote:It would probably be possible to put the reloading logic into the main images, so that it was possible to reload under program control in a way similar to what you are saying, but as this is really Dave/Jason's baby, I'll leave it to them as to whether this is something that they want to pursue - it certainly would be quite a major code change.
Ok. So I wouldn't have to keep fiddling under the computer I was wondering about putting an extension cable on the DIP switches - then wondered about connecting them to a 74xx latch with a bit of decoding logic!

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Tue Feb 10, 2015 1:29 pm

jgharston wrote:Going through the code, I can't see any reason for pointing the INTs to the RAM copy of the Tube Client, especially as as soon as anything gets booted it get overwritten. And if it was for a putative full-1024K RAM version, then why not copy it underneath itself at the top of memory, as other CoPros do? All 16-bit 80x86 environments reserve the top of memory for the host interface code, so that's where it should be.
The reason at the interrupt handling needs to be in RAM is because the LX9 Co Pro uses NMI for data transfer, rather than DMA. The "Client ROM" NMI handling code is self-modifying so needs to run from RAM. I think this is moot once DOSPLUS has booted, as it has it's own interrupt handling, so this is just to load the boot loader.

I think the Acorn 286 also used NMI rather than DMA.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by firthmj » Tue Feb 10, 2015 7:02 pm

TheCorfiot wrote:Hi Dave

Thanks for knocking some sense into my brain lol.
Ok, that explains the 0 or 1 state, so 0 0 0 0 is supposed to be the original 65c102 ext Ram core.

Problem is that is not what appears on the screen, I get the Acorn 6502 banner, and the different speed cores dont seem to be accessible....Help

:)
I should have made it clearer that in the MCS file I uploaded, I put the old ROM in the 0000 design, and the new ROM in the 1000 - 1011 design.

So if you have the switches set to 0000 (I think as they would have been when you received it), you should get the "Acorn 6502 Tube 64K" banner.

If you then put the DIP switch furthest from the 40-pin connector on, you should get the 65c102 banner, and the CoPro should be running at 32MHz.
If you then put the DIP switch at the opposite end on as well, you should still have the same banner, but running at 16 MHz.

Does this match the behaviour you are seeing?

Regards

Michael
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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by TheCorfiot » Tue Feb 10, 2015 7:49 pm

AhHa....

Thanks Michael, i will try it out later and get back to you but it does all make sense now..

if i get the 65C102 Banner then its using internal ram and overclockable..
if i get the 6502 Banner then its the std 4mhz ext ram core.

Cheers
:)

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by DutchAcorn » Wed Feb 11, 2015 6:09 am

With the Z80 processor the Format command doesn't work right for my setup.

It often hangs early in the formatting process, from which it can recover using ctrl-break.

If it succesfuly formats a disc (and asks to format another one or return to CP/M), it also hangs and will not recover using ctrl-break (flashing Mode 7 cursor in the top left of the screen).

Any ideas? I have not reflashed my copro yet.
Paul

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by TheCorfiot » Thu Feb 12, 2015 12:54 am

OK Feedback time :)

I have been extensively testing both 6502 cores (Int and ext ram) at all speeds too.

Using Elite as a Benchmark but also the classic Planets Animation program as it carries out lots of Maths functions.

Beeb used is the heavily upgraded Econet, 1770DFS, Speech, 12 Rom board, WE 32K Ram Card machine...

Using the std ext ram core which now displays the Acorn Tube 6502 banner the system is rock stable, enjoyed quite a few games of Elite and Planets runs fine...
It seems much more stable using the old 6502 Tube Rom code.

Using the newer Int Ram Ram cores which display the Acorn 65C102 banner the system fails to initialise Elite to the point you get the rotating ship at any speed.
It also falls over at any speed when running the Planets program.
It draws everything fine but at the point goes to plot the background stars it halts.
But boy the speed of drawing those planets and lines is Phenomenal.

Could I be so bold Matthew and ask if you could rebuild your cores using the Acorn Tube 6502 Rom code to see if that makes any difference, I will of course continue testing.

On another point for Jason, reading through the thread, you mention adding 2 decoupling capacitors to the board to cure the instability issues, my boards only have the one capacitor, is it worth me adding another ?

Thanks guys
:)

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Thu Feb 12, 2015 6:56 am

TheCorfiot wrote:Using the newer Int Ram Ram cores which display the Acorn 65C102 banner the system fails to initialise Elite to the point you get the rotating ship at any speed.
Interesting; this was not my experience with the initial version of the "fast" core. I haven't tried Micheals version yet. Michael, did you manage to test with Elite?
TheCorfiot wrote: It also falls over at any speed when running the Planets program.
It draws everything fine but at the point goes to plot the background stars it halts.
But boy the speed of drawing those planets and lines is Phenomenal.
How do I run this program?
TheCorfiot wrote: Could I be so bold Matthew and ask if you could rebuild your cores using the Acorn Tube 6502 Rom code to see if that makes any difference, I will of course continue testing.
I would be very surprised if this is a software difference. It's much more likely to be hardware related.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by DutchAcorn » Thu Feb 12, 2015 7:59 am

DutchAcorn wrote:With the Z80 processor the Format command doesn't work right for my setup.

It often hangs early in the formatting process, from which it can recover using ctrl-break.

If it succesfuly formats a disc (and asks to format another one or return to CP/M), it also hangs and will not recover using ctrl-break (flashing Mode 7 cursor in the top left of the screen).

Any ideas? I have not reflashed my copro yet.
Also tried using a Winchester drive (Adaptec board) using JGH's driver. That hangs on startup if the Winchester is connected (does not boot to C:).
Anyone tried this using a cheese wedge?
Last edited by DutchAcorn on Thu Feb 12, 2015 8:21 am, edited 1 time in total.
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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Thu Feb 12, 2015 8:15 am

Michael and Bas,

I've just tried Michael's lx9_20150208_firthmj.mcs Xilinx MCS file.

I'm able to at least start Elite at 4, 8 and 16MHz, but not at 32MHz. So it does look like there are some issues to resolve. I'm having other random stability issues as well at 32MHz.

The mode of failure in Elite was a * appearing in the top left hand corner after the program had loaded. I also saw this in my original design when I tried to push it beyond 37.7MHz.

I've looked carefully at how you are doing the clocking, and it looks absolutely correct to me. The only slight difference from my version is the way the parasite Tube clock is generated. In my case, it is "not cpu_clken" in your case it is a separate signal synchronous signal "p_tube_clk".

I'm wondering if your arrangement is more susceptible to clock skew, because two different clock nets are involved. It's possible Xilinx tools are handling "not cpu_clken" with less skew, because of the following feature:
The clock pin (CLK) has an individual inversion option. The clock signal can be active at the negative edge of the clock or the positive edge for the clock without requiring other logic resources. The default is at the positive clock edge
I just went back to my original 37.7MHz design, and this seems to run Elite OK. Maybe this is just luck rather than anything else.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Thu Feb 12, 2015 8:24 am

DutchAcorn wrote:With the Z80 processor the Format command doesn't work right for my setup.

It often hangs early in the formatting process, from which it can recover using ctrl-break.

If it succesfuly formats a disc (and asks to format another one or return to CP/M), it also hangs and will not recover using ctrl-break (flashing Mode 7 cursor in the top left of the screen).

Any ideas? I have not reflashed my copro yet.
I've just tried this a couple of times, and not had any problems.

The last change to the Z80 Co Pro was 18th December, so you probably have the latest hardware version.

Can you describe you Beeb configuration?

Could someone else test the Z80 FORMAT command?

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by TheCorfiot » Thu Feb 12, 2015 10:11 am

Hi Dave

Thanks so much for looking into the issues..
It's odd that even with a heavily loaded Beeb the copro is stable with the extram core but not the intram core, i just felt by using common rom code we could remove any unnecessary variables to help debug the problems.

i have a welcome disc image with the planets program i will upload for you soon.

and tonight i will test disc formatting with the z80 core :)

For the record i have tested disc format, read and write operations with the 6502 extram core and all is fine. :)

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by danielj » Thu Feb 12, 2015 10:58 am

I've formatted discs with the z80 core and not had any problems.

d.

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by DutchAcorn » Thu Feb 12, 2015 11:03 am

hoglet wrote:Can you describe you Beeb configuration?
It's a BBC B Issue 7 and is fitted with Steve Picton's RAM/ROM board. 8271 FDC. DNFS 1.2. Dual 5.25" floppy drive, powered from the Beeb. No econet. That's it :D

Oh, and it has the Z80 copro fitted, but you may have guessed that. 8)

I used the FORMAT command that is on Disc 1 of the Z80 installation discs.
Paul

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Thu Feb 12, 2015 12:12 pm

DutchAcorn wrote:It's a BBC B Issue 7 and is fitted with Steve Picton's RAM/ROM board. 8271 FDC. DNFS 1.2. Dual 5.25" floppy drive, powered from the Beeb. No econet. That's it :D
Has anyone else run successfully with a 8271? I'm using a 1770.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by firthmj » Thu Feb 12, 2015 12:59 pm

hoglet wrote:Michael and Bas,

I've just tried Michael's lx9_20150208_firthmj.mcs Xilinx MCS file.

I'm able to at least start Elite at 4, 8 and 16MHz, but not at 32MHz. So it does look like there are some issues to resolve. I'm having other random stability issues as well at 32MHz.

The mode of failure in Elite was a * appearing in the top left hand corner after the program had loaded. I also saw this in my original design when I tried to push it beyond 37.7MHz.

I've looked carefully at how you are doing the clocking, and it looks absolutely correct to me. The only slight difference from my version is the way the parasite Tube clock is generated. In my case, it is "not cpu_clken" in your case it is a separate signal synchronous signal "p_tube_clk".

I'm wondering if your arrangement is more susceptible to clock skew, because two different clock nets are involved. It's possible Xilinx tools are handling "not cpu_clken" with less skew, because of the following feature:
The clock pin (CLK) has an individual inversion option. The clock signal can be active at the negative edge of the clock or the positive edge for the clock without requiring other logic resources. The default is at the positive clock edge
I just went back to my original 37.7MHz design, and this seems to run Elite OK. Maybe this is just luck rather than anything else.

Dave
I've also seen some stability issues at 32MHz - even just loading HIBASIC from ADFS. As you say, it doesn't seem to happen at 16MHz.

In earlier versions of my design, I didn't have the "multi-term" versions of the lower speed clock versions, and those wouldn't boot at all. I theorised that this was due to either the 6502 core or the Tube interface module having a problem with the clock being high for more than one clock cycle - hence the arrangement I ended up with.

I suspec that using "not cpu_clken" as the clock for the Tube interface won't work when cpu_clken has a non 1:1 ratio, but it might be worth trying that.

I guess the other option is to try and get the whole parasite design to run synchronously, when the Xilinx tools will take care of the timing requirements, without needing to feed the Tube module with an inverted clock.

Regards

Michael
Had fun at the
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Meeting 21st September 2019

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Thu Feb 12, 2015 11:13 pm

Hi all,

I've merged Michael's 6502Fast Co Pro changes into github, and fiddled a bid. It seems to be stable at the moment at all clock speeds (with the Elite test).

One other addition I made was to update the boot message to one of:
- Acorn TUBE 04MHz 65C102 Co-Pro
- Acorn TUBE 08MHz 65C102 Co-Pro
- Acorn TUBE 16MHz 65C102 Co-Pro
- Acorn TUBE 32MHz 65C102 Co-Pro
based on the switch settings, so that it's clear which speed it's currently running at.

Bits are in github.

After a few more people have tested this, we can cut another .mcs file at the weekend.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by danielj » Fri Feb 13, 2015 8:00 pm

I realise I can probably piece my way through this, but I fear frying something... Would someone be kind enough to post a quick précis of the process from compiling the HDL files (I think I can do this, but I can't find where the bit file is so perhaps I'm not?) to testing individual files via the programmer (not entirely sure what I'm doing here) through to building the mcs file and uploading that?

Even just a very quick overview and a few pointers would be useful! :)

Yours cluelessly,
d.

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Fri Feb 13, 2015 8:23 pm

Daniel,

Do you have version 14.7 of the Xilinx ISE tools installed?

If not, start downloading it now, as it's many GB is size.

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Fri Feb 13, 2015 8:37 pm

There are three things you could might consider as "programming" in the Xilinx world:

1. Downloading a single Co Pro design .bit file into configuration "RAM" on the LX9. This would allow you to try out a new design, but is not re-programming the ROM, so powering down will get you back to the original. Programming takes about 3 seconds.

2. Programming a single-boot .mcs file containing a single Co Pro design into FLASH. This will replace everything you already have, and will survive a power cycle. Programming takes about 60 seconds.

3. Programming a multi-boot .mcs file containing many Co Pro designs into FLASH. This will replace everything you already have, and will survive a power cycle. But it's pretty involved making the .MCS file. Programming takes about 5-10 minutes.

I'd suggest focussing on (1) until you get abit more familiar with ISE (the compiler that generates a .bit file), and iMPACT, the programmer software.

Are you using Windows or Linux?

Dave

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by danielj » Fri Feb 13, 2015 9:08 pm

Hi Dave,
Downloaded ISE 14.7, managed to make a bit file and transfer it across now :) - running it all on windows. - So that's 1) that I've got down.

Not really sure how to get it set up to use the flash (or even make sure it's the right type of flash). I appreciate I have to "combine" the bit files together so they end up residing at the correct addresses so the dip switch settings can select them.

Happy to go through a website to get the hang of it, I just want to make sure I'm selecting the right things :?

d.

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Re: Matchbox sized 6502 / Z80 / 6809 Co Pro

Post by hoglet » Fri Feb 13, 2015 9:28 pm

danielj wrote:Not really sure how to get it set up to use the flash (or even make sure it's the right type of flash). I appreciate I have to "combine" the bit files together so they end up residing at the correct addresses so the dip switch settings can select them.
In iMPACT, programming the FLASH involves:

- Double click on "Boundary Scan"

- Right click the select "Initialize Scan Chain"

- Click OK on the "Device Programming Properties" dialog

- Double click on the little box above the Green Xilinx Chip that is labelled SPI/BPI

- Select the .mcs file you want to program

- You should then get a "Select Attached SPI/BPI Dialog", make sure the following are selected, then click OK
-- SPI PROM
-- S25FL032P
-- Data Width: 1

- Single click on the SPI/BPI box - it should turn green, and on the left you should now see the following options:
-- Program
-- Verify
-- Erase
-- Blank Check
-- Readback
-- Get Device Checksum
-- Read Device Status

- Double clock on Program

- Click OK in the "Programming Properties" dialog (the defaults are fine)

- You should now see a progress dialog, and depending on the size of the .mcs file, between 1 min and 10 mins later, it should say "Programming Successful"

The tricky bit is building the multiboot .mcs file

Try this with one posted on the forums...

I'll rebuild one now from the latest designs, and post it later....

Dave

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