flynnjs wrote:I was thinking &ffee won't modify as it's a well known entry point / os call so that could be a write only shadow.
You can't use anything outside the &FEFx range, as all other addresses are written to on startup to copy the ROM to RAM. And some code does
modify locations in the MOS entry block at &FFxx, such as my Tube Atom/System environment
which puts an Atom/System entry block at &FFxx.
Doing some investigations, none of the Tube Status registers are ever written to from the parasite side by any client code. Without detailed investigation I don't know if they are even writeable
. Only Status1 contains bits that are directly modifiable (the control bits) and they are only modifiable from the host side, all the other registers just contain the TxRdy/RxRdy flags in b7 and b6. So, that is four I/O locations with six bits in each for reading, and four I/O location with 8 bits for writing.
The client code and memory map reserves 16 bytes for I/O, but there are only 8 Tube registers in TUBE+0 to TUBE+7 at &FEF8 to &FEFF on the 6502, and the hardware is wired to only respond to TUBE+0 to TUBE+7. So, that leaves another 8 bytes free for I/O at TUBE-8 to TUBE-1 at &FEF0 to &FEF7.
(Years ago I sketched up something that you could plug multiple CoPros into and it decoded an address in the host's TUBE+8-15 range at &FEF8-F to decide which CoPro was seen in the TUBE+0-7 range. Of course, that doesn't conflict with anything in the parasite, so TUBE-8 to TUBE-1 at &FEF0-&FEF7 are free, and also recognised as being reserved and not trampled on by the standard client code.)
So, from the parasite side, there are 8 bytes and 4 x 6/8 bits available for I/O from the parasite:
&FEF0 (TUBE-8) b7-b0
&FEF1 (TUBE-7) b7-b0
&FEF2 (TUBE-6) b7-b0
&FEF3 (TUBE-5) b7-b0
&FEF4 (TUBE-4) b7-b0
&FEF5 (TUBE-3) b7-b0
&FEF6 (TUBE-2) b7-b0
&FEF7 (TUBE-1) b7-b0
&FEF8 (TUBE+0) (&FEF0) b5-b0 for reading, b0-b7 for writing
&FEFA (TUBE+2) (&FEF2) b5-b0 for reading, b0-b7 for writing
&FEFC (TUBE+4) (&FEF4) b5-b0 for reading, b0-b7 for writing
&FEFE (TUBE+6) (&FEF6) b5-b0 for reading, b0-b7 for writing
I once toyed with the idea of adding some sort of extra I/O to a 6502 CoPro with careful cutting of a track near IC4. Not sure what I was thinking of putting there, maybe some blinkenlights. But that was probably at the back of my mind when I sketched up a recommended 6809 CoPro design and suggested putting an ACIA at TUBE+8/9. (I thought it was on this diagram
I had the 16-byte I/O addresses the wrong way around above. I've been coding the 6809 client most of the day which has &FEEx(*
) for I/O with the Tube registers in the first
eight bytes. But while the 6502 also has 16 addresses reserved for I/O, at &FEFx, the Tube registers are in the second
eight bytes at &FEF8-&FEFF. Edited the above to match reality.
(*)The reason the 6809 doesn't also use &FEF
x is because the hardware vectors are mapped to &FEFx by toggling A8 to move them away from &FFFx.