ATOM FPGA

discussion of games, software, hardware & emulators relating to the Acorn Atom and Acorn System machines.
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hoglet
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Re: ATOM FPGA

Post by hoglet » Wed May 07, 2014 6:26 pm

I used a cheap eBay Arduino one, piccie here:
http://www.stardot.org.uk/forums/viewto ... =30#p73069

It's wired in to an extra header I piggy-backed onto the Arcade mega wing.

Dave

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Re: ATOM FPGA

Post by PhilYoung » Sat May 10, 2014 8:03 am

hoglet wrote:Hi Phil,

I've spotted the probably cause of this.

I was referring to SPI_PORT rather than SPI_Port.

It seems ISE 14.2 is sensitive to this, and ISE 14.4 is not.

Can you try again with the latest code?

Are you using the Papilio? The latest compiled bitstream is here:
https://github.com/hoglet67/AtomFpga/bl ... apilio.bit

Dave
Sorry for the delay in replying, I had to wait until being re-activated after changing email address.

It turns out that the 'papilio' version compiles OK in the earlier version, but I had tried the 'olimex mod-vga' version which still doesn't work. Looking a bit more closely, I noticed that on the project hierarchy the SPI appears as a little VHL icon in the working version and a '?' in the non-working one. So I re-added the SPI.VHDL source file which corrected that, and it now runs correctly. So it must have been something like a broken link in the project file.

I don't have a Papilio or a mod-vga, but I do have a Terasic DE1. This has a larger FPGA and all the hardware gubbins, so I'm hoping to modify the source to run on that. It was used for Mike Sterlings BBC-on-FPGA, so that should be a good template to follow. Since I know little of VHDL this might take a while....

Cheers,

Phil Young

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Re: ATOM FPGA

Post by hoglet » Sat May 10, 2014 9:31 am

Phil,

The DE1 looks like an excellent board, and has everything needed (and more) including on-board SRAM and FLASH. Most of the Atom functionality is in Atomic_core and the VHDL here is pretty generic RTL VHDL.

You'll need to create a new top level VHDL module that's specific to your DE1, that contains:
- Atomic_core
- clock generation for 12.5875MHz (VGA), 16MHz (Core) and 32MHz (SID) clocks.

Use Atomic_top.vhd as your starting point, as this uses external SRAM, which is what you have in the DE1.

The tricky part will be the clock generation from the available 24MHz, 27MHz and 50MHz clocks. You'll have to use the Altera PLL clock generation to generate the required inputs. e.g. Using the 24MHz clock the following seem plausible:
  • 12.5875MHz ~= 24MHz * 11 / 21
  • 16MHz = 24MHz * 4 / 6
  • 32MHz = 24MHz * 4 / 3
One thing I should look at doing is to externalize the ROMs, so that these can use external components if available (like on the DE1). This would make the software updates much easier!

Maybe I should look at procuring a DE1 as well - you can't have too many FPGA Boards. :D

Dave

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Re: ATOM FPGA

Post by PhilYoung » Sat May 10, 2014 10:20 am

hoglet wrote:Phil,

The DE1 looks like an excellent board, and has everything needed (and more) including on-board SRAM and FLASH. Most of the Atom functionality is in Atomic_core and the VHDL here is pretty generic RTL VHDL.

You'll need to create a new top level VHDL module that's specific to your DE1, that contains:
- Atomic_core
- clock generation for 12.5875MHz (VGA), 16MHz (Core) and 32MHz (SID) clocks.

Use Atomic_top.vhd as your starting point, as this uses external SRAM, which is what you have in the DE1.

The tricky part will be the clock generation from the available 24MHz, 27MHz and 50MHz clocks. You'll have to use the Altera PLL clock generation to generate the required inputs. e.g. Using the 24MHz clock the following seem plausible:
  • 12.5875MHz ~= 24MHz * 11 / 21
  • 16MHz = 24MHz * 4 / 6
  • 32MHz = 24MHz * 4 / 3
One thing I should look at doing is to externalize the ROMs, so that these can use external components if available (like on the DE1). This would make the software updates much easier!

Maybe I should look at procuring a DE1 as well - you can't have too many FPGA Boards. :D

Dave
Hi,

I'm a bit busy at the moment so it might take a while, but hopefully the VHDL should be directly transferable, thanks for the pointers about the clocks. I wonder if it would run on a DE0-nano (with additional hardware), quite a few people seem to have these for the John Kortink 6502 co-pro.

I got my DE1 from mouser http://uk.mouser.com/Search/ProductDeta ... y993-P0528, you need to add VAT to the price. It also runs a version of Arkanoid, as seen here: https://www.youtube.com/watch?v=X6O-ELLtzx4. It comes with a very old version of the Quartus IDE though, so you'd probably want to download an up-to-date one.

Cheers,

Phil Young

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Re: ATOM FPGA

Post by hoglet » Sat May 24, 2014 3:42 pm

Hi all,

I've started work on an Atom Wing for the Papilio One. The Papilio is my preferred FPGA board at the moment, as it's fairly cheap and contains a on-board USB-connected programmer which works well with Linux as well as Windows.

Before I got too far along with this, I thought I would post a few details for feedback and to see if anyone has any suggestions for improvements.

The Wing will have:
- 128Kx8 Static RAM (AS6C1008)
- 128Kx8 FLASH (SST39VF010, in system programmable for the brave!)
- SD Card slot
- VGA Connector
- PS/2 Connector
- 3.5mm Stereo Jack
- Reset Switch

By using external RAM and ROM, I'm hoping sufficient resources will be freed up in the FPGA to have room to add an Arduino AVR Soft Core running Phill's AVR AtomMMC firmware. Any maybe also some of the Atom GODIL VGA features as well.

The RAM and ROM are large so that I can implement a ROM Box like Phill's RAM ROM card.

One of the limiting factors is the Papilio One has only 48 I/O pins, and I'm now using them all:
- RAM and FLASH (A0...16, D0..7, RAMCE, RAMOE, RAMWE, ROMCE, ROMOE, ROMWE)
- SD Card slot (DI, IO, CS, CLK)
- VGA Connection (R0..1, G0..1, B0..1, VS, HS)
- PS2 (CLK, DATA)
- Audio (L, R)
- Reset Switch (RST)

Here's the board schematic and board layout so far:
HogletAtomWingV1a.zip
(56.16 KiB) Downloaded 73 times
AtomWing1.png
AtomWing2.png
The board is currently 3.75" x 3.75", and the track density will be pushing the limits of my single sided PCB production process.

There are a few signals above that are somewhat superfluous: RAMCE, ROMCE, R0 and B0. Wondering whether to add a second PS/2 Port for a mouse.

Also wondering whether to add a switch to select between Atom and BBC memory maps, although this could be done from software (or the PS/2 Keyboard hardware).

Finally, if I'm going to be playing with the Arduino AVR Soft Core for AtomMMC, then Uart Rx and Tx might be useful for debugging.

Feedback welcome!

Dave

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Re: ATOM FPGA

Post by oss003 » Sat May 24, 2014 9:27 pm

Hi Dave,

is it an option to use SPI external RAM/ROM instead of normal RAM/ROM to free some I/O lines?

Greetings
Kees

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Re: ATOM FPGA

Post by sirmorris » Sat May 24, 2014 9:54 pm

looks awesome! what a great idea :D

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Re: ATOM FPGA

Post by 1024MAK » Sat May 24, 2014 11:01 pm

hoglet wrote:RAMCE, RAMOE, RAMWE, ROMCE, ROMOE, ROMWE
Is there any reason why the SRAM and the FLASH cannot share /WE and /OE, with selection being done by /RAMCE and /ROMCE?

Mark

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Re: ATOM FPGA

Post by hoglet » Sun May 25, 2014 6:51 am

sirmorris wrote:looks awesome! what a great idea :D
Thank you Charlie!

Actually I need to talk to you (and Phill) about the AtomMMC firmware and the possibility of including either a binary blob, or a copy of the sources in the AtomFPGA GitHub.
oss003 wrote: is it an option to use SPI external RAM/ROM instead of normal RAM/ROM to free some I/O lines?
I think it might just about be technically possible, as these devices are getting faster and faster. But we would need a controller designed to make them look like a legacy SRAM. Most controllers I have seen are more tuned for block transfer than random access. Also, one of my goals is to keep the core of AtomFpga compatible with a wide range of development boards. Very few contain SPI RAM.
1024MAK wrote: Is there any reason why the SRAM and the FLASH cannot share /WE and /OE, with selection being done by /RAMCE and /ROMCE?
I think there are two ways to reduce the number of RAM/ROM control signals from 6 to 4:
- RAMOE, ROMOE, RAMWE, ROMWE
- RAMCE, ROMCE, WE, OE
Both should work - can you (or anyone) think of a reason for using one or the other?

I think I can free up a total of 4 I/Os: two from the RAM/ROM control signals and two from the VGA interface. Two of these would get used to add an RS232 (2 lines) for debugging the AVR. The remaining two would allow a second PS/2 connector for a mouse, as I'm planning to back-port some of the Atom GODIL features.

Thanks for the input, keep it coming!

Dave
Last edited by hoglet on Thu Mar 12, 2015 7:55 am, edited 1 time in total.

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Re: ATOM FPGA

Post by 1024MAK » Sun May 25, 2014 7:58 am

The only other ways that I can think of to free up more I/O pins, is to either latch some of the address lines to the SRAM and the FLASH ROM (the 8 highest ones), or multiplex the data and address buses (most or all of the address lines). Of course the more complex it becomes, means more extra logic and buffers :(

I think just latching the top eight address lines generates sufficient spare lines at the expense of one additional control line (so freeing 7 I/O pins) and this would need just one octal latch chip.

I've run two octal latch chips from a parallel printer port (of a 8 bit computer, and in this case, no not a Acorn computer) before when I needed 16 output lines. I used the strobe line direct to the clock input on one octal latch and via an inverter to the clock input on a second octal latch. With careful programming, it did what I wanted (but of course it was not the fastest 16 bit port in the world :lol: ).

Mark

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Re: ATOM FPGA

Post by hoglet » Sun May 25, 2014 9:14 pm

Small update....

I've realized that the Papilio has a USB port, which can also be used as a serial port. In fact, this is where the serial port of the Arduino AVR8 Soft Core is connected. So that's two pins no longer needed.

I've had a play with the Arduino AVR8 Soft Core, and managed to synthesise it and compile a small test C program that flashes the LEDs and writes to the serial port. All from Linux with a proper make file. Cool or what!

It turns out the Arduino AVR8 Soft Core implements an ATMega103, and which is different to the ATMega644p Phill used in the AVR AtomMMC. I'm very new to this world, so I have no idea if this is a show stopper or not.

After a bit of tweaking of a few IO register names, I was able to get Phill's code to compile and produce some output on the serial terminal.
AVR1.png
Hopefully there will be more progress tomorrow....

Dave

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Re: ATOM FPGA

Post by eric » Tue May 27, 2014 9:17 pm

Interersting setup ..

I follow this with excitement ...
Take out all the old hardware and build in one card with all on it ... hmmm ..

shortage on I/O hmm..... is spi port expanders an idea ?


Question :
You cannot use half of its internal ram for the atom memory map ?

Grx..

Eric

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Re: ATOM FPGA

Post by hoglet » Wed May 28, 2014 7:22 am

Hi all,

Another small progress update, and answers for eric.

At the weekend did a bit more work on the VHDL:
- re-factored so that the RAM and ROM were both outside of the core
- added a generic to the core to allow the SID to be disabled
- added a generic to the core to allow the SDDOS SPI to be disabled
- created a new top level design that includes the Arduino AVR8 Soft Core (16K internal ROM and 4K internal RAM).

I was able to synthesis this and it easily fits in the device (phew!)

The one remaining bit of work is to include Phill's CPLD design that interfaces the Atom to the AVR8. I'll need port this to VHDL, and re-work it slightly so it becomes a fully synchronous, driven from the 16MHz clock. But the function will stay exactly the same.

In terms of I/O, I've reduced the VGA port to 1 Red, 2 Green, 1 Blue (just like the GODIL), and run the two freed up lines to the PS/2 socket. This means that with a PS/2 splitter you could plug in a keyboard and an mouse. For now, I'm keeping the RAM/ROM section with 6 control lines, because I can't be bothered to re-layout that bit of the PCB.

I happy with this as an initial version, so I plan to build a prototype this weekend.
eric wrote:Interersting setup ..

I follow this with excitement ...
Take out all the old hardware and build in one card with all on it ... hmmm ..
I'm not sure what Alan D's motivation for starting this project was. Alan?

For me, it's just for fun of playing with FPGAs again. I don't really think of this as any kind of an upgrade for the original Atom hardware. But as Atoms become rarer over time, FPGA implementations will keep the experience alive a bit longer.

The biggest outstanding issue is that the use of a PS/2 keyboard means the physical keyboard layout is very different to the original Atom, making most games tricky to play. Maybe there is some scope to improve this. Phill, in your Atom Clone, what did the keyboard layout end up like?
eric wrote: shortage on I/O hmm..... is spi port expanders an idea ?
It might be, but then we would have to write software specifically for this, which I don't think would happen (too few users). The Atom GODIL (my other FPGA project) also suffers from this problem. The hardware is done, but there is no software for the new features.
eric wrote: Question :
You cannot use half of its internal ram for the atom memory map ?
I'm not sure I understand this thought. Can you expand a little more?

If you mean use the FPGA internal Block RAM, there is 40K, but the Arduino AVR8 Soft Core we're adding for AtomMMC will need half of this.

Dave

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Re: ATOM FPGA

Post by eric » Wed May 28, 2014 9:14 pm

Hi Dave,

I thought that the dev board you use has enough RAM onboard to use as system memory map for the atom that you emulate on it .. or is that not usable in that way ?

and why the arduino ? as a soft core on it ?

But I must be honest .. my knowledge of FPGA's is practically non-existent .. so maybe you must not take my questions and idea's all too serious ..

Grx..

Eric

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Re: ATOM FPGA

Post by hoglet » Wed May 28, 2014 9:54 pm

Hi Eric,
eric wrote:I thought that the dev board you use has enough RAM onboard to use as system memory map for the atom that you emulate on it .. or is that not usable in that way ?
I'm using the Papilio One which is very basic and has no on-board RAM, other than what inside the FPGA.
eric wrote: and why the arduino ? as a soft core on it ?
It's so I can add version of AtomMMC (which uses either a PIC or an AVR processor to interface to a FAT file system on a SD Card). Ironically this will use more FPGA logic than the rest of the Atom put together.

Keep the questions coming!

Dave

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Re: ATOM FPGA

Post by eric » Wed May 28, 2014 10:05 pm

Hi Dave,

I understand the concept of what this project is about now a bit better ..

External ram on an add on board .. not using ram inside the fpga .. (I thought it was possible to load RAM objects into fpga's ... size depending on the capacity of the fpga.. )

Grx..

Eric

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Re: ATOM FPGA

Post by hoglet » Thu May 29, 2014 8:07 am

eric wrote:Hi Dave,

I understand the concept of what this project is about now a bit better ..

External ram on an add on board .. not using ram inside the fpga .. (I thought it was possible to load RAM objects into fpga's ... size depending on the capacity of the fpga.. )
You are right, there is memory inside the device that can be used as RAM or ROM.

This project supports several different FPGA boards (and hopefully more over time). The current version for the Papilio One uses the standard Arcade Wing for I/O. This works without any external RAM/ROM, but uses all 40K (20x2K) of the internal block RAMs in the Xilinx device on the Papilio:
- C000-FFFF ROM - 8 block RAMs
- 0000-07FF RAM - 1 block RAMs
- 2000-3FFF RAM - 4 block RAMs
- 8000-9FFF RAM - 4 block RAMs
- Atom SID - 2 block RAMs
- 6847 Line Doubler - 1 block RAM
- 6847 Char ROM - 1 block RAM (but actually synthesised as logic)
Total 21 block RAMs

I wanted to add AtomMMC support (i.e. the AVR core which needs 16K ROM and 4K RAM, which would be a further 10 block RAMs). I also wanted to add a full 32K of lower text RAM (another 11 block RAMs) on the Atom side. So clearly there is not enough room for all this. The best answer is to push the Atom lower test RAM and ROM outside of the device.

We'll still continue to support the standard configuration, and also the Olimex MOD VGA 32K that Alan uses. So, everyone is happy!

Dave

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Re: ATOM FPGA

Post by hoglet » Mon Jun 02, 2014 8:32 pm

Hi all,

Here's some pictures of the Papilio Atom Wing prototype, which was this weekends project (aka obsession as my other half says).

The two socketed chips are a 128Kx8 RAM and an 128Kx8 ROM:
IMG_0558.JPG
I had a lot of fun actually getting it to do anything at all! There were three separate faults, two broken tracks (very close to the RAM socket), and a fault with the PLCC socket meaning that A10 was not connected. The latter took me ages to find. I ended up having to debug the reset sequence and realized the although the address bus correctly output FFFC FFFD, the data coming back from the ROM was actually the data in FBFC FBFD.
IMG_0561.JPG
Here's a couple pictures showing how the Papilio FPGA board and the Atom Wing mate together
IMG_0562.JPG
IMG_0564.JPG
IMG_0565.JPG
It lives!!!
IMG_0567.JPG
And AtomMMC, running on the AVR core can read the card!
IMG_0568.JPG
But all is not quite perfect:
IMG_0569.JPG
There are a few things that might be amiss, that Phill and Kees might be able to help with.

I've had to re-work the "PL8 CPLD" logic, as the T65 core is fully synchronous. So, I could have introduced some bugs, that subtly affect how the Atom and AVR talk to each other. The current VHDL is here.

Another possibility is an incompatibility between the latest 2.9.5 version of AtomMMC (here) and the PIC/AVR firmware. Phil, any chance you could post the AtomMMC ROM you are using so I can check what I'm compiling is the same?

Yet another possibility is I've messed something up on the AVR hardware side. I had to make quite a few changes to the FPGA core to allow it to be embedded in another design, and the external interrupt controller "mod" had several bugs in it.

Anyway, I have the AVR serial console available for debugging (running at 57600 baud), and I can compile and reload the AVR firmware in about 10 seconds, so it's fast to try lots of things.

Any ideas on what to look for?

The ERROR - INVALID OBJECT seems to mean "file not found", correct?

Dave

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Re: ATOM FPGA

Post by hoglet » Mon Jun 02, 2014 8:38 pm

Here's the Reset sequence, from the AVR's point of view:

Code: Select all

stdio initialised
compiled at 20:57:11 on Jun  2 2014
SerialPort0
cmd=FE res=55
cmd=FE res=AA
cmd=FE res=55
cmd=80 res=02
cmd=F0 res=FF
The simplest thing I can do that doesn't work properly is
*INFO MENU

Code: Select all

cmd=21 cmd=11 res=40
cmd=22 res=40
cmd=20 res=A9
Here's what you see on the Atom:
IMG_0570.JPG
Here's a hex dump of the start of the MENU file

Code: Select all

000000 4d 45 4e 55 00 00 00 00 00 00 00 00 00 00 00 00
000010 00 28 00 28 c5 08 a9 94 8d 0a 02 a9 fe 8d 0b 02
000020 20 0e 2c 4e 4f 4d 4f 4e 0d a0 04 20 e1 2b 20 0e
000030 2c 4c 4f 41 44 20 4d 4e 55 41 2f 53 50 4c 41 53
000040 48 0d 20 e3 ff c9 41 90 f9 c9 47 b0 f5 8d 58 28
The load address should be read from 0x10 and 0x11, it actually seems to be coming from 0x26 and 0x27.

Any ideas?

Dave

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Re: ATOM FPGA

Post by hoglet » Mon Jun 02, 2014 9:13 pm

A bit more debugging added to the AVR:

Code: Select all

stdio initialised
compiled at 22:05:18 on Jun  2 2014
SerialPort0

-- Reset
LaL=00, La=00
cmd=FE res=55
LaL=10, La=00
LaL=00, La=00
cmd=FE res=AA
LaL=10, La=00
LaL=00, La=00
cmd=FE res=55
LaL=10, La=00
LaL=00, La=00
cmd=80 res=02
LaL=10, La=00
LaL=00, La=00
cmd=F0 res=FF
LaL=10, La=00


-- *INFO MENU

-- Command 21 = CMD_INIT_WRITE

LaL=00, La=00
cmd=21 LaL=03, La=03
LaL=03, La=03
LaL=03, La=03
LaL=03, La=03
LaL=03, La=03

-- Command 11 = CMD_FILE_OPEN_READ

LaL=00, La=00
cmd=11 res=40
LaL=10, La=00
LaL=01, La=01

-- Command 22 = CMD_READ_BYTES

LaL=00, La=00
cmd=22 res=40

-- Command 20 = CMD_INIT_READ
LaL=10, La=00
LaL=00, La=00
cmd=20 res=A9  -- This should be the start of the file, but it's actually 0x16 bytes in
LaL=10, La=02
Data = 94  
LaL=10, La=02
Data = 8d
LaL=10, La=02
Data = 0a
LaL=10, La=02
Data = 02
LaL=10, La=02
Data = a9
LaL=10, La=02
Data = fe
LaL=10, La=02
Data = 8d
LaL=10, La=02
Data = 0b
LaL=10, La=02
Data = 02
LaL=10, La=02
Data = 20
LaL=10, La=02
Data = 0e
LaL=10, La=02
Data = 2c
LaL=10, La=02
Data = 4e
LaL=10, La=02
Data = 4f
LaL=10, La=02
Data = 4d
LaL=10, La=02
Data = 4f
LaL=10, La=02
Data = 4e
LaL=10, La=02
Data = 0d
LaL=10, La=02
Data = a0
LaL=10, La=02
Data = 04
LaL=10, La=02
Data = 20
LaL=10, La=02
Data = 00
Looks to me like AtomMMC is trying to read the 22 byte ATM Header (starting at offset 0), but that the AVR is for some reason returning 22 bytes, starting at offset 22. Stranger and stranger. :shock:

Dave

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Re: ATOM FPGA

Post by sirmorris » Tue Jun 03, 2014 5:34 am

FAB! :lol: :lol: Super work - I look forward to making one of my own!

As for the error -could the internal file buffer reads be mis-aligned because of some 32 byte buffer/ram block address boundary restriction or other or something?

A bit random - sorry. It's early <yawns>

C

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Re: ATOM FPGA

Post by oss003 » Tue Jun 03, 2014 6:25 am

Hi Dave,

WOW Dave, another outstanding job done ..... =D> =D>
hoglet wrote:The ERROR - INVALID OBJECT seems to mean "file not found", correct?
If I read the PIC software correct, in FF.C there are three reasons for an INVALID OBJECT error:

Code: Select all

if (!fs || !fs->fs_type || fs->id != id)
        return FR_INVALID_OBJECT;
If the file doesn't exist, you should get a NOT FOUND error so there's probably something wrong in the fs-structure of MENU or the fs-structure is misread.

Greetings
Kees

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Re: ATOM FPGA

Post by oss003 » Tue Jun 03, 2014 6:31 am

Hi Dave,
hoglet wrote:Looks to me like AtomMMC is trying to read the 22 byte ATM Header (starting at offset 0), but that the AVR is for some reason returning 22 bytes, starting at offset 22. Stranger and stranger. :shock:
Could it be that the command byte $22 is still in the latch?

Greetings
Kees

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Re: ATOM FPGA

Post by hoglet » Tue Jun 03, 2014 7:27 am

sirmorris wrote:As for the error -could the internal file buffer reads be mis-aligned because of some 32 byte buffer/ram block address boundary restriction or other or something?
Charlie, I've tried page aligning the globalData buffer and it made no difference.
oss003 wrote:Could it be that the command byte $22 is still in the latch
Kees, I don't think the confusion is the left over command $22 acting as an offset, because the incorrect offset is 22 decimal ($16).

Below is even more debugging from the AVR, where after each command I'm dumping the contents of the 256 byte globalData buffer.

This complete sequence is *INFO MENU

Where it goes amiss is cmd $22, where instead of reading the ATM header from offset 0, it reads it from offset $16 (22 decimal), which is also the number of bytes being asked to be read.

If fact, looking at the PIC code, I don't see how random access into a file is even possible.

Here's the code implementing command $22 (CMD_READ_BYTES)

Code: Select all

void wfnFileRead(void)
{
   UINT read;
   if (globalAmount == 0)
   {
      globalAmount = 256;
   }
   log0("File Read GA = %d\n", globalAmount);
   WriteResult(STATUS_COMPLETE | f_read(&fil, globalData, globalAmount, &read));
}
It's like f_read is somehow getting executed twice.

Stranger and stranger :shock: :shock: :shock:

Unfortunately, I have to go to work now :cry:

Code: Select all

LaL=00, La=00
cmd=21 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
LaL=03, La=03
LaL=03, La=03
LaL=03, La=03
LaL=03, La=03
LaL=03, La=03
LaL=00, La=00
cmd=11 res=40
4d 45 4e 55 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
LaL=01, La=01
LaL=00, La=00
cmd=22 File Read GA = 22
res=40
a9 94 8d 0a 02 a9 fe 8d 0b 02 20 0e 2c 4e 4f 4d 
4f 4e 0d a0 04 20 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
LaL=00, La=00
cmd=20 res=A9
LaL=10, La=02
Data = 94
LaL=10, La=02
Data = 8d
LaL=10, La=02
Data = 0a
LaL=10, La=02
Data = 02
LaL=10, La=02
Data = a9
LaL=10, La=02
Data = fe
LaL=10, La=02
Data = 8d
LaL=10, La=02
Data = 0b
LaL=10, La=02
Data = 02
LaL=10, La=02
Data = 20
LaL=10, La=02
Data = 0e
LaL=10, La=02
Data = 2c
LaL=10, La=02
Data = 4e
LaL=10, La=02
Data = 4f
LaL=10, La=02
Data = 4d
LaL=10, La=02
Data = 4f
LaL=10, La=02
Data = 4e
LaL=10, La=02
Data = 0d
LaL=10, La=02
Data = a0
LaL=10, La=02
Data = 04
LaL=10, La=02
Data = 20
LaL=10, La=02
Data = 00

User avatar
hoglet
Posts: 8678
Joined: Sat Oct 13, 2012 6:21 pm
Location: Bristol
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Re: ATOM FPGA

Post by hoglet » Tue Jun 03, 2014 7:31 am

hoglet wrote: It's like f_read is somehow getting executed twice.
Bugger me, that's exactly what is happening...

Code: Select all

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
LaL=01, La=01
LaL=00, La=00
cmd=22 File Read Read=-21994, GA = 22
fread
res=40
fread
a9 94 8d 0a 02 a9 fe 8d 0b 02 20 0e 2c 4e 4f 4d 
4f 4e 0d a0 04 20 00 00 00 00 00 00 00 00 00 00 
It's a bug in the debugging macro :lol:

Code: Select all

#define WriteResult(value) 	{ if (DEBUG_RESULT) log0("res=%02X\n",value); Wr
iteDataPort(value); }

User avatar
hoglet
Posts: 8678
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Re: ATOM FPGA

Post by hoglet » Tue Jun 03, 2014 7:39 am

And now it's working perfectly, and I can run the AtoMMC archive!!!

:D :D :D :D :D :D :D

Charlie, Phil, do you have any objections if I add the AtomMMC firmware code into the AtomFPGA Git repository?

Dave

User avatar
oss003
Posts: 3124
Joined: Tue Jul 14, 2009 11:57 am
Location: Netherlands
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Re: ATOM FPGA

Post by oss003 » Tue Jun 03, 2014 8:52 am

Hi Dave,

congratulations with the birth of a new Atom clone ....... =D> :wink:

Greetings
Kees

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sirmorris
Posts: 774
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Location: oxfordshire uk
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Re: ATOM FPGA

Post by sirmorris » Tue Jun 03, 2014 9:12 am

I have no objections at all. Phill?

It would be nice if the revision history was maintained as I tried to do when I put the V2.x < 2.9 code in the retrosoftware HG repo.

Phill - do you have zips with the older versions in?

Prime
Posts: 2798
Joined: Sun May 31, 2009 11:52 pm
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Re: ATOM FPGA

Post by Prime » Tue Jun 03, 2014 10:49 am

sirmorris wrote:I have no objections at all. Phill?

It would be nice if the revision history was maintained as I tried to do when I put the V2.x < 2.9 code in the retrosoftware HG repo.

Phill - do you have zips with the older versions in?
I'll check....

Cheers.

Phill.

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sirmorris
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Re: ATOM FPGA

Post by sirmorris » Tue Jun 03, 2014 6:08 pm

FWIW the AtoMMC 2.X (where x < 9) repository is here:

http://www.retrosoftware.co.uk/hg/AtoMMC/

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