W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

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roland
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W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Sat Nov 16, 2019 7:01 pm

(Edit: splitted from the Yarrb topic)

I have a breakthrough on the AtoMMC with a WD65C02: after writing to #B40x the bits A0...A3 are latched. So writing to #B401 will latch the value #1. This works this way with a 6502 in the Atom (on the Yarrb board). But with the WD65C02 the latch does not hold this value. As soon as the LATCH signal goes down, the latch contents go to 0.

IMG_3987.JPG
Yellow: Latch 0 output (pin 16)
Blue: LATCH signal (pin 13)

Now I just have to figure out why it behaves like this with just another CPU :-k

In another topic Hoglet has posted this test program:

Image

This test program fails on every read operation. But what is the use of reading ?#B402? The 2 is not latched because it only tatches on write and the address lines do not go into the PIC. The PIC sees the value of the last write, in this case that's 0. So couldn't line 70 be X=?#B400 ? BTW I only have this diagram of the AtoMMC, is there a more recent version somewhere?
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Re: YARRB [SOLD OUT]

Post by roland » Sun Nov 17, 2019 12:31 am

I think that the problem is that the 74LS75 is not edge triggered and hat the address bus of the WD65C02 is too fast. If there is an edge triggered equivalent then that might solve it. The symbol on the circuit diagram shows an edge triigered device but the data sheet mentions that the output follows the input as long as the gate / control is at a high level.

Using a (not pin compatible) 74LS175 might solve this issue. I will try that one of thse days.
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Re: YARRB [SOLD OUT]

Post by hoglet » Sun Nov 17, 2019 8:10 am

roland wrote:
Sun Nov 17, 2019 12:31 am
I think that the problem is that the 74LS75 is not edge triggered and hat the address bus of the WD65C02 is too fast.
So it seems the current design needs RnW to change *before* the address bus changes.

Edit: this is not correct, the current design does correctly use Phi2. It's failing just because the delay through 2x 74LS139 is much larger than the W65C02S's address hold time (of 10ns-30ns).

I'm not convinced a rising edge triggered version (74LS175) would work. It depends if the address bus is stable when RnW falls.

What I would try is connecting Phi2 to pin 13 of IC1 (after bending it out).

Edit: This is a dumb/incorrect suggestion!

You may also need to use faster versions of the 74xx139.

Edit: Yes, try this first!

Dave
Last edited by hoglet on Sun Nov 17, 2019 10:43 am, edited 3 times in total.

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Re: YARRB [SOLD OUT]

Post by hoglet » Sun Nov 17, 2019 10:08 am

hoglet wrote:
Sun Nov 17, 2019 8:10 am
What I would try is connecting Phi2 to pin 13 of IC1 (after bending it out).
Actually, even then the timing is marginal...

The W65C02S address bus changes between 10ns and 30ns after the falling edge of the clock.

So (worst case) there is only 10ns after the clock edge to release the latch signal, and a 74LS139 is much slower than this.

I think you also need a much faster 74xx139, such as a 74AC139 or a 74F139.

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Re: YARRB [SOLD OUT]

Post by roland » Sun Nov 17, 2019 10:14 am

I will try a 74F139 as I have a few spares of them. Unfortunately SirMorris has soldered the chips directly on the board, no sockets for the the 74LS139 and 74LS75 :(
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Re: YARRB [SOLD OUT]

Post by hoglet » Sun Nov 17, 2019 10:23 am

roland wrote:
Sun Nov 17, 2019 10:14 am
I will try a 74F139 as I have a few spares of them. Unfortunately SirMorris has soldered the chips directly on the board, no sockets for the the 74LS139 and 74LS75 :(
On further reflection, the fix I suggested above (connect Phi2 to IC1 pin 13) is wrong and unnecessary, as the WR signal already incorporates Phi2.

So a much faster 74xx139 may well work.

(In fact, I see Charlie actually used a 74AC139 on the schematic)

Dave

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Re: YARRB [SOLD OUT]

Post by 1024MAK » Sun Nov 17, 2019 12:00 pm

For those following who don’t get it:

Yeah, the 74LS75 is behaving as per the datasheet. If the inputs change before the enable input goes high to low, the outputs will follow the current state of the inputs prior to the enable input changing state. The 74LS75 is a transparent latch.

The problem is the design of the circuit. As Dave suggests, either the control signal to the enable pin of the 74LS75 has to be switching much sooner (less propagation delay via the 74x139) or a different circuit is needed. One that is less dependent on the address bus holding a valid value after the inputs to the address decoding & control circuitry have processed the signal.

It’s always slightly tricky latching the state of the address bus especially if the system can run at different clock speeds.

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Re: YARRB [SOLD OUT]

Post by hoglet » Sun Nov 17, 2019 12:23 pm

1024MAK wrote:
Sun Nov 17, 2019 12:00 pm
It’s always slightly tricky latching the state of the address bus especially if the system can run at different clock speeds.
I think it's actually better to latch the address bus in the middle of the cycle, using the rising edge of Phi2. Then you are not fighting hold time problems.

That said, the original MOS6502 (for which AtoMMC was originally designed) holds the address for 80ns-100ns after Phi2.

So in that context Charlie's design is very reliable.

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Re: YARRB [SOLD OUT]

Post by 1024MAK » Sun Nov 17, 2019 1:38 pm

hoglet wrote:
Sun Nov 17, 2019 12:23 pm
I think it's actually better to latch the address bus in the middle of the cycle, using the rising edge of Phi2. Then you are not fighting hold time problems.
Yes, especially for designs which use the W65C02, that’s a better method.
hoglet wrote:
Sun Nov 17, 2019 12:23 pm
That said, the original MOS6502 (for which AtoMMC was originally designed) holds the address for 80ns-100ns after Phi2.

So in that context Charlie's design is very reliable.
Yes, please note that my comments above should be taken in context. Charlie's design was intended for existing Atom systems using NMOS 6502 CPUs and the design he used is absolutely fine for these.

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Sun Nov 17, 2019 1:44 pm

First of all, and you all probably know it, that this topic is not intended to break or to condemn Charlie's design. He did a real good job when he designed the AtoMMC which brought many of us lots of joy. The original design was for an Atom with a "classic" 6502 or a R65C02 and that works excellent. The people who put an incompatible Western Digital W65C02 in their Atom are to blame, it's the same as placing a 8086 in the Atom and start complaining that it does not work :mrgreen:

Having said that, I discovered that I don't have a 74F139 (it was a 74F138) but I did try it with a 74HCT139. Again, no luck. So I did replace the 74LS75 by a 74LS175 and now it latches the address bits:
IMG_3988.JPG
Yellow: latch signal (clock)
Blue: O3 of the latch (= A3 latched)
This signal was generated by:

Code: Select all

STA #B400,X
INX
JMP #5000
So latching the address bits works now. But the AtoMMC still does not :(
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by hoglet » Sun Nov 17, 2019 1:51 pm

roland wrote:
Sun Nov 17, 2019 1:44 pm
So latching the address bits works now. But the AtoMMC still does not :(
Relating this to the previous conversation, the 74LS175 is positive edge triggered. The latch signal will go high in the middle of the write bus cycle (~40ns after Phi2 goes high), which is the perfect place to latch the write address.

So it's quite a surprise that AtoMMC doesn't work.

What does the earlier test program do now?

Dave

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Sun Nov 17, 2019 2:42 pm

The test program fails now at every address, the value read back is the last value written to #B400: #20. If I change that value in line 50 I read back that value.

Also the heartbeat test fails now:

Code: Select all

?#B400=#FE;DO PRINT &?#B400;UNTIL 0
now returns only #FE (again, last written value)... :?:
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by hoglet » Sun Nov 17, 2019 2:52 pm

What happens if you put the NMOS 6502 back?

The 74LS175 has a very different pinout to the 74LS75 - any chance of a wiring mistake?

It might be worth posting a photo.

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Sun Nov 17, 2019 3:25 pm

hoglet wrote:
Sun Nov 17, 2019 2:52 pm
What happens if you put the NMOS 6502 back?
Pin 19 of the NMOS 6502 broke :oops:
Placing a NMOS 6502 now has the same results like the W65C02.
hoglet wrote:
Sun Nov 17, 2019 2:52 pm
The 74LS175 has a very different pinout to the 74LS75 - any chance of a wiring mistake?
It might be worth posting a photo.
I am double checking the wiring....
.... one moment please ....
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Sun Nov 17, 2019 3:43 pm

It works \:D/

I had one wire wrong: O2, pin 2 of the 74LS175 went to the socket's pin 8 instead of pin 16 #-o
Now the MMC works with both the NMOS6502 and the W65C02 :D
IMG_3993.JPG
The current setup....
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by 1024MAK » Sun Nov 17, 2019 7:03 pm

👍 =D> :D

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by hoglet » Sun Nov 17, 2019 8:01 pm

Yes, fantastic work there Roland.

Are you still planning try a 74F139 in combination with the original 74LS75?

This might be slightly easier for other's to replicate than your mod. :D

Dave

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Sun Nov 17, 2019 8:07 pm

Actually I did reverse my changes and put both the 7475 and the NMOS 6502A back into the Atom because the W65C02 has more troubles than joy at 2 MHz. When I order new parts I can order a 74F139 just to see how it behaves.....
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by KenLowe » Mon Nov 18, 2019 12:06 am

hoglet wrote:
Sun Nov 17, 2019 8:01 pm
Yes, fantastic work there Roland.
Ageed. =D> =D> =D>
hoglet wrote:
Sun Nov 17, 2019 8:01 pm
Are you still planning try a 74F139 in combination with the original 74LS75?

This might be slightly easier for other's to replicate than your mod. :D

Dave
A little daughter board to hold the 74LS175 and do the pin translation might be another solution.

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Mon Nov 18, 2019 6:22 am

KenLowe wrote:
Mon Nov 18, 2019 12:06 am
A little daughter board to hold the 74LS175 and do the pin translation might be another solution.
That would be a good solution but I don't think it's worth the effort. After all, who is using the W65C02 CPU? My experiences with this specific CPU model is that it does not work well in both the Yarrb board and also not in the Atom2k18 (which does not suffer from this problem because the logic of latching is in a CPLD).

However, if there is any interest in such a conversion board, just let me know and I will create one. But it is not necessary for the normal "classic" NMOS or CMOS 6502(A) cpu's.

Perhaps Charlie can replace the 74LS75 with a 74LS175 when he ever makes a new design of the AtoMMC board. But as he just did make a new design I don't expect that to happen really soon :wink:
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by sirmorris » Mon Nov 18, 2019 12:42 pm

I think this is a great idea. I am working actively on a new board so this would work perfectly.

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Mon Nov 18, 2019 1:00 pm

If you're working on a new board, can I make some extra suggestions?
  • make the 20p header in such a position that we can solder a female connector on it so that it goes directly to PL8 without a flat cable
  • IMHO it must also be possible to route tracks between the PIC and the SD card holder and still make it easy to split the board in two parts. You could make a row with holes with tracks between them. The 10p headers are optional that way and only needed if the card holder goes outside of the Atom.
With those two adjustments it must be easier to fit the AtoMMC board at the (PL8) solder side of the Atom.
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by janrinze » Tue Nov 19, 2019 8:32 pm

How does the w65c816 fare with this?
I remember we tried these a long time ago but could not get them working reliably.

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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by roland » Tue Nov 19, 2019 10:23 pm

I really don't know how the 65C816 (from whatever manufacturer) will fare. My statement is that it is not supported :mrgreen:
I Don't have one and I never looked to the pin out to check if it can be installed in the 6502 socket.
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Re: W65C02S6TPG-14 and AtoMMC (split from YARRB [SOLD OUT])

Post by Prime » Wed Jan 01, 2020 4:39 pm

Right can confirm that the replacement of the LS75 with LS175 allows the AtoMMC to work with the WD65C02 CPU.

One thing I did find however is that the WD CPU is even more fussy about the 8255 that it will work with than the NMOS version. In the end I ended up using an NEC D71055, which is compatible with the 8255 but rated to 10MHz and uses CMOS tech. I suspect that a CMOS 8255 would also work.

The other thing I found is that with a 70ns video RAM, I needed to shorten it's write cycle otherwise the contents get corrupt on write, mainly due to the chip always being read enabled and the timing at the end of the write cycle meaning that the address lines change before the write line is released (due I think to propogation delays) This isn't a problem with the slower RAMS e.g. old 6264s and 2114s as the RAM doesn't see the change before it ends the write, but new faster ones it causes a problem. This is true of the NMOS 6502 too with fast RAMS, though the write delay needed seems to need to be longer for the NMOS, as it sheems to have a longer setup time for the Data lines.

P1000581.JPG
Test Atom board with WD65C02
Cheers.

Phill.

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