I've been working on a few things today:
These are all now pushed to github.
1. Multiple LED modes
The Knight Rider was beginning to annoy me, so I've made it more useful.
There are now four modes for the LEDs (and it would be easy to add more in the future):
- Mode 0: Displays the value in the LED_Data_Register (#BFE1)
- Mode 1: Displays Knight Rider (linked to the instruction execution speed)
- Mode 2: Displays the high byte of the CPU address bus
- Mode 3: Displays the low byte of the CPU address bus
The mode is selected by bits 1..0 of the LED_Ctrl_Register (#BFE0)
The push switches on the FPGA module increment/decrement the mode as well. The switches are properly debounced:
https://github.com/hoglet67/AtomFpga/bl ... bounce.vhd
2. Turbo Mode
Turbo mode from bits 6,5 of #BFFE is now wired up. If you are using the PS/2 keyboard, pressing F1..F4 should also update the mode. I think there might be a bug with this in certain cases.
3. Clocking and 8MHz operation
I've changed the main clock from 16MHz to 32MHz, which has fixed the issues with the 8MHz turbo mode (?#BFFE=96). I'm using -55 RAM and -70 FLASH and this seems quite stable.
The only remaining work is to add wait states when the external bus is accessed at 4MHz (1 wait state) or 8 MHZ (3 wait states). That would give the bus a maximum speed of 2MHz.
4. Investigate a reset bug
I discovered that hitting break when a SID is playing causes a very nasty crash. Even re-initializing the FPGA doesn't fix it.
The bug only happens when using the PS/2 keyboard and is related to reset on the 6522 (when it's generating timer interrupts).
When using the matrix keyboard, pressing break generates a reset, and everything is fine. But when using the PS/2 keyboard, pressing break (F10) only resets the 6502 in the FPGA. This is because the NRST pin of the FPGA is currently an input.
I think the fix is to do the following:
- redefine the NRST pin as bidirectional
- during power up reset, the FPGA should pull NRST low
- when the PS/2 keyboard is selected and F10 is pressed, the FPGA should pull NRST low
- at other times NRST should be "Z" (high impedance) and operate as an input
- remove C24 (10uF)
Removing the C24 capacitor is really just a precaution, as it's quite a lot of capacitance for the FPGA to try to discharge.
Are you happy if I make this change tomorrow Roland?
I don't have plans for anything else beyond what's outlined in this post.