roland wrote: ↑
Tue Mar 12, 2019 8:13 am
The 6522 has quite a large access time: 150ns for a 2 MHz device and even 300ns for a 1 MHz device. Will that ever work? I doubt it if we need fast RAM and ROM..... If that is a problem I might consider to get the CPU out of the FPGA (i.e. start all over again with a new design).
First, let's think about the Atom, as that's the primary target.
Although the internal system clock is 16MHz, a clock enable signal is used on the 6502 core so it is only actually clocked 1 in N cycles:
- N=16 gives a 1MHz Atom
- N=8 gives a 2MHz Atom
- N=4 gives a 4MHz Atom
- N=2 gives an 8MHz Atom
The address and control signals that the 6502 outputs stay stable until the next clock enable. So in effect, it is being clocked slowly.
(It's done this way because it's easier to design reliable FPGAs if everything runs off a single global clock, without any nasties like clock gating or stretching, etc. It's also what all the design tools need to be able to perform an accurate timing analysis.)
Now, the Atom only needs fast RAM/ROM to support running at 8MHz (same as a real Atom would). At 2MHz, there is approximately 500ns where the external address bus is stable, so it should be possible to connect a real 6522 and make this work. We just need to generate appropriately timed external Phi clock (which is not currently done but would be easy to add).
So I think it's no problem to run with a real 6522 externally, or in fact run with any original Atom device connected to the PL6/7.
Now, in 8MHz mode if the external bus ran at 8MHz then much not would actually work reliably, but that's no worse than a real Atom. In fact, it's still better: the 8255 is internal, so the system will be stable and usable. Only the 6522 might not work reliable.
One solution would be to use a faster 6522, e.g. a W65C22 which can run at 14MHz. Another approach would be to design some logic to add wait state(s) where accessing slow external devices. That's part of the fun of this approach. You can start simple and incrementally make improvements / add new features without have to design a new PCB each time. I think you would loose that if you switched to plan B with a real 6502.
Now In terms of the Beeb, I don't think it would be possible to share the external bus between the SRAM and the 6522, as the SRAM is active all the time. So I think that limits you to using BeebFpga as it currently is, with both 6522s internal, and any external 6522 disabled. I don't see a problem with that.
Edit: And I think plan B would preclude the Beeb use case entirely.