Bitshifters - Ode to Mode 7 Competition

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dp11
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Re: Bitshifters - Ode to Mode 7 Competition

Post by dp11 » Sat Sep 17, 2016 7:58 pm

Once tidied up very easy to create a split screen.

MODE 5(4 colours) top half of the screen could perhaps take 5K Ram and the bottom half take 0.5K (mode 7 , 8 colours)


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jms2
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Re: Bitshifters - Ode to Mode 7 Competition

Post by jms2 » Sat Sep 17, 2016 9:47 pm

Awesome work! I think this is genuinely the first time this has been done on the beeb. =D> =D> =D>

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kieranhj
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Re: Bitshifters - Ode to Mode 7 Competition

Post by kieranhj » Sat Sep 17, 2016 9:53 pm

The compo does say "use & abuse of the MODE 7 character mapped display" so I think this counts. Would be a good showcase. What could be done with it?!
Bitshifters Collective | Retro Code & Demos for BBC Micro & Acorn computers | https://bitshifters.github.io/

dp11
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Re: Bitshifters - Ode to Mode 7 Competition

Post by dp11 » Sun Sep 18, 2016 8:02 pm

Lots of minor improvements .
Still more things to do .

Code: Select all

\\ mode5 / mode7 split screen by Dominic Plunkett
\\ based on rupture code below

\\ This is source code to accompany the Vertical Rupture wiki article by Richard Talbot-Watkins
\\ found at http://www.retrosoftware.co.uk/wiki/index.php/How_to_do_the_smooth_vertical_scrolling

\\ The code is adapted from the BBC micro ssd disk image:  http://www.retrosoftware.co.uk/wiki/images/2/25/Rupture1.zip
 

\\ The original code was in BBC asm and largely uncommented.

\\ The code below is for use with BeebASM (http://www.retrosoftware.co.uk/wiki/index.php/BeebAsm)

\\ All I have done is to restructure the code very slightly
\\ and comment it by pasting in excerpts from Richard's wiki article.
\\ I found that this made the code easier to follow and aided
\\ my understanding of the wiki article.  I hope that it helps you too!

\\ For completeness, the zip file you've downloaded
\\ contains a (BUILD.bat) batch file which assembles the code below and merges the output ssd disk image
\\ with the accompanying template.ssd.  The template.ssd contains the BASIC
\\ program which changes to MODE 2 and plots the boxes/text as seen in the wiki article screenshot.

\\ jbnbeeb. July 2015.

MACRO STOREI	addr,val
	LDA #val
	STA addr
ENDMACRO

MACRO STORE16I addr,val
	LDA #val AND 255
	STA addr
	IF (val AND 255 ) != (val DIV 256)
		LDA #(val DIV 256)
	ENDIF	
	STA addr+1
ENDMACRO

MACRO STR6845  reg,val
	STOREI &FE00,reg
	STOREI &FE01,val
ENDMACRO

MACRO STR6845scraddr  val
	STR6845  12,(val DIV 256)
	STR6845  13,(val AND 255)
ENDMACRO

ORG &70

  .oldirq 		SKIP 2
  .vsync 		SKIP 1
  .whichtimer 	SKIP 1
 
 ; vertical timings we need 312 rows
 ; graphicrows * 8 ; this must end on a multiple 10  unless we want misshapen mode 7 chars(5,10,15,20,25)
 ; telerows * 10 ; 
 ; blanking ( 6*10) ( inlcude vsync of two chars)
;			  2*10 rows End of frame 	
 ;            2*10 rows Vsync
;			  2*10 rows top of frame		
 ; Row adjust 2
 
  graphicrows = 15 ; valid numbers 5, 10,15,20,25
  telerows  = ((312-2 -60 - (graphicrows*8)) /10) ;13 ; 
 
  timerwait1=5*8*64
  timerwait2=(graphicrows-1)*8*64 - 64
 
ORG &2000
.start

;--------------------------------------------------
.Main
;--------------------------------------------------
	jsr InitIRQandCRTC
RTS

;--------------------------------------------------
.InitIRQandCRTC
;--------------------------------------------------
\\ ** We disable unwanted interrupts
\\    and enable vsync, and Timer 2 System VIA interrupts only.
\\ This code is only called once.

	SEI
		LDA #&7D   ; disable all System VIA interrupts bar vsync
		STA &FE4E

		LDA #&A0   ; Timer 2  VIA interrupts.
		STA &FE6E
		
		STORE16I &FE68 , &FFFF  ; Timer 2

		STOREI &FE6B , 0  \\ ACR
		STOREI &FE6C , 4  \\ PCR

		LDA &204
		STA oldirq
		LDA &205
		STA oldirq+1
		
		\\set interrupt vector to address of our irq handler below
		LDA #irq AND 255:STA &204
		LDA #irq DIV 256:STA &205

	CLI
RTS

;--------------------------------------------------
.irq  
;--------------------------------------------------
\\** This is the IRQ handler **
\\ It is called each time an interrupt is generated.

	LDA &FE4D ;IFR
	AND #2
	BEQ timer
		\\** If we're here, it's a vsync interrupt.**
		
		;STA &FE4D 
		STA whichtimer 
		
		\\Set T2 timer with  wait1 value
		STORE16I &FE68 , timerwait1

		\\ load new screen start addr in R12,R13
		STR6845scraddr &5800/8
		
		STOREI &FE20 , &C4  \\ mode 5
	
		STR6845 8, 1  ; interlace
		STR6845 9, 7  ; scanlines per character
		STR6845 2, 49 ; horizontal sync position
		
		\\Now we must wait until the new CRTC cycle has started. We already know this to take 5 character rows (remember?!).
		\\5 character rows
		\\= 40 (5*8) scanlines
		\\= 2560 (40*64) 1MHz clock ticks
		
.exitRTI		 
		LDA &FC ; when an interrupt is generated, content  of A register
				; is put in addr &FC. We therefore restore this value to A
				; before exiting interrupt handler.

		JMP (oldirq)
RTI

.timer
		\\** if we're here, it's a timer interrupt. **
		LDA &FE6D
		AND	#&20
		BEQ exitRTI
		LDA whichtimer
		BEQ secondtimer
		
		\\Set T2 timer with  wait2 value
		STORE16I &FE68 , timerwait2

		LDA #0	
		STA whichtimer		
		
		\\We are now into a new CRTC cycle. The CRTC has taken its internal address pointer from R12/R13 and is currently refreshing the screen from somewhere between &5800 and &8000 (whatever we specified - we are choosing this address for our scrolling after all!)
		
		\\ Next we do a few cunning things:
		
		\\(See P.359 of Advanced User Guide for explanation of CRTC registers)
		
		;specifying a total CRTC cycle length of graphicrows rows. (for the top half of screen)
		STR6845 4 , graphicrows-1
		
		;We set R7 to anything greater than graphicrows. This ensures that VSync will NEVER be generated during this cycle. This is what we want, as we know from the PAL standard that we must have 39 rows in a refresh, and generating VSync every 16 rows will clearly cause the TV to barf! Let's set R7 to 255 just to make a point :)
		
		STR6845 7 , 255
		
		;We set R6 to 255: this ensures that we see all the rows of this CRTC cycle; this is what we want - they are all valid after all. Of course we could equally set R6 to anything higher than 16; it won't display any more because there are only 16 rows in the whole CRTC cycle!
		
		STR6845 6 , 255
	
		;  We set R12/R13 to look at &7c00. As we know, the CRTC has already cached its internal address pointer from R12/R13 this update and changing them mid-update won't affect its screen address pointer. However, as we know, this update is only going to last 16 rows, at which point its cycle will start all over again, and its screen address pointer will be re-cached, this time using the NEW values in R12/R13, i.e. &7c00!
		
		STR6845scraddr (&7c00-&7400)EOR&2000

		\\Now we need to wait for the new CRTC cycle to begin - this will of course be in graphicrows character rows time from the last cycle:
		
		LDA &FC  ; when an interrupt is generated, content  of A register
				 ; is put in addr &FC. We therefore restore this value to A
				 ; before exiting interrupt handler.
		JMP (oldirq)		 
	RTI

	.secondtimer	 
		\\ swap to mode 7
		STOREI &FE20 , &4B
	
		STR6845 8, &93		; interlace
		STR6845 9, 18  ; scanlines per character
		STR6845 2, 52 ; should be 51 horizontal sync position
		
		\\ If we're here,
		\\ we've begun refreshing static bit of screen (from &7C00)
		\\ so...
		\\....The trick now is to restore normal conditions again. 
		
		\\(See P.359 of Advanced User Guide for explanation of CRTC registers)
		
		STR6845 4 , telerows + 2 +3 ; total rows (-1)
		
		STR6845 5 , 2 ; screen adjustment ***
		
		;We set R6 to 16 to ensure that we only plot 16 rows.
		
		STR6845 6 , telerows ; displayed rows
		
		;We set R7 such that VSync is generated at the same point relative to the end of the CRTC cycle as a normal MODE 7 refresh.
		
		STR6845 7 , telerows +2 ; sync position
		
		\\And that's pretty much it! The VSync generated then takes us back to the beginning of this loop, upon which we do the same thing all over again.

		STOREI &FE6D, &20 ; clear timer IRQ		

		LDA &FC  ; when an interrupt is generated, content  of A register
				 ; is put in addr &FC. We therefore restore this value to A
				 ; before exiting interrupt handler.
	JMP (oldirq)
	RTI
.end

SAVE "VRUPT", start, end

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lurkio
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Re: Bitshifters - Ode to Mode 7 Competition

Post by lurkio » Sun Sep 18, 2016 9:07 pm

Any chance you could put it on .SSD for those of us who are clueless about building with BeebAsm, etc.?

:oops: [-o<

dp11
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Re: Bitshifters - Ode to Mode 7 Competition

Post by dp11 » Sun Sep 18, 2016 9:23 pm

Attached.

After *VRUPT Most interrupts are disabled currently , so the keyboard won't work. You can reenable them with ?&FE4E=&F3, but the screen will become jittery .

You can add new code after *VRUPT e.g MODE 5 PRINT" some top text" :MODE 7:PRINT" some bottom text"

Timing isnt perfect yet
Attachments
New WinRAR ZIP archive.zip
MODE5/MODE7
(648 Bytes) Downloaded 43 times

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lurkio
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Re: Bitshifters - Ode to Mode 7 Competition

Post by lurkio » Sun Sep 18, 2016 10:28 pm

Thanks but what are you running this on?

It won't work for me either in BeebEm or JSBeeb or a real BBC B or a real Master!

The screen jumps and goes blank.

:?

Here's the JSBeeb link:
:?:

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Re: Bitshifters - Ode to Mode 7 Competition

Post by dp11 » Mon Sep 19, 2016 6:25 am

Can you change mode2 to mode5 in runme? Thanks.

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lurkio
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Re: Bitshifters - Ode to Mode 7 Competition

Post by lurkio » Mon Sep 19, 2016 9:12 am

Ah, yes. Thanks. That works now.
1.jpg
Screenshot
The MODE 7 scrolling wraparound seems a bit off, but I guess that's part of the tidy-up?

Very nice!

=D>

dp11
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Re: Bitshifters - Ode to Mode 7 Competition

Post by dp11 » Mon Sep 19, 2016 9:17 am

Scrolling isn't supported ( i'll have a think :) )

Lots of of other bits of fix to do.

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Re: Bitshifters - Ode to Mode 7 Competition

Post by dp11 » Mon Sep 19, 2016 9:18 am

I thought it was quite neat to be able to do MODE 5 and setup the top half , then Mode 7 to setup the bottom half

hexwab
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Re: Bitshifters - Ode to Mode 7 Competition

Post by hexwab » Tue Sep 27, 2016 3:51 am

Here's a MODE 7 overscan thingy I made a few months ago but never got round to polishing. I don't have any good screens for it, nor did I ever get the OS to be happy writing to a non-contiguous memory layout. Still possibly of interest?

Tom.
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simonm
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Re: Bitshifters - Ode to Mode 7 Competition

Post by simonm » Sat Jan 21, 2017 12:13 pm

Hello again folks! Time flies, and the date we put on this little mode7 compo has come around quicker than we thought.
In all honesty, with RL and all that even Kieran and I havent finished our demo for this yet (although its coming along nicely!)
We're probably going to extend this for a bit longer anyway, but just wondered how many folks are thinking of contributing something?

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