Proposed: "The Ultimate Electron Upgrade"

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by fordp » Wed Jun 12, 2019 9:06 pm

https://youtu.be/24ehoo6RX8w
I just watched this and it made me think of this thread!
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Thu Jun 13, 2019 2:38 am

fordp wrote:
Wed Jun 12, 2019 9:06 pm
I just watched this and it made me think of this thread!
That's PCBWay! They do the TinyFPGA boards, I believe.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by daveejhitchins » Thu Jun 13, 2019 9:34 am

fordp wrote:
Wed Jun 12, 2019 9:06 pm
https://youtu.be/24ehoo6RX8w
I just watched this and it made me think of this thread!
Ah! The one I posted above :wink: It is worth the second post, in case anyone missed it . . .

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by daveejhitchins » Thu Jun 13, 2019 7:26 pm

Initial BoM costing come to £56.18 - We should be able to get that down a little by shopping around. Maybe down to £50. The build and testing has still to be priced in!

Initial BoM costing come to £30.64 - We should be able to get that down a little by shopping around. The build and testing has still to be priced in!

Attached is the Preliminary updated spreadsheet.

Dave H :D
UEU BoM 13-6-19.xlsx.zip
(13.54 KiB) Downloaded 10 times
Edit: Repost of Spreadsheet and corrected the costings leaving the old one there. See next post - D'oh!
Last edited by daveejhitchins on Thu Jun 13, 2019 10:19 pm, edited 1 time in total.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Thu Jun 13, 2019 9:18 pm

daveejhitchins wrote:
Thu Jun 13, 2019 7:26 pm
Initial BoM costing come to £56.18 - We should be able to get that down a little by shopping around. Maybe down to £50. The build and testing has still to be priced in!
I found a good discount... change the VAT calculation to add 20% rather than 120% :D

That brings VAT down to £5.107 and the per-unit cost to £30.64, which is in line with my ballpark estimate. Very curious to see build and test quotes!
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by daveejhitchins » Thu Jun 13, 2019 10:13 pm

Aaaaa! That's what happens when you set-up spreadsheets when your tired - Good catch, thanks. I've reposted the spreadsheet and reposted the totals.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Sun Jun 16, 2019 1:41 pm

On the programming front... the debug microcontroller is alive, and with the FPGA configured to pass its SPI port straight through to the serial flash chip, I've successfully called the device ID command and verified that it's alive (I get EF 17, which is what the W25Q128JV datasheet says to expect). So that's three chips at least superficially working -- the FPGA, the microcontroller, and the serial flash :)

Next job will be to verify that the FPGA can see all the ULA pins, and once I find my logic analyzer, to see if the clock generation is working.
Last edited by myelin on Sun Jun 16, 2019 1:42 pm, edited 1 time in total.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by daveejhitchins » Sun Jun 16, 2019 2:36 pm

There just aren't enough =D> in the world :D

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Wed Jun 19, 2019 3:30 pm

All pins checked, some RTL tweaks made... one chip replaced, which I managed to solder on backwards the first time (which explains the puff of smoke and USB over current error I got the first time I plugged it in!)... PHI0 and CSYNC are looking good. Just about time to try it out in a real machine :)

(Will have to wait until tomorrow as I have to head to work now!)
1E9A44D6-6BBF-4E67-80FA-B207C2F32F4D.jpeg
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by daveejhitchins » Wed Jun 19, 2019 6:53 pm

Is it tomorrow yet . . .? :roll: :-

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by Ramtop » Wed Jun 19, 2019 8:01 pm

All I can say is =D>
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by Elminster » Wed Jun 19, 2019 8:06 pm

Even if it doesn't work, it will still look good.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by mr-macrisc » Wed Jun 19, 2019 8:29 pm

Fingers and toes still crossed 😂

Wasnt gonna post this but ah feck it... Why the hell cant i dream...

Impressive isn't even close.

Is it too soon to start dreaming. Ap5, plus1, plus 3, beeb compatible rom, even master compatible rom? Maybe nula? Or maybe beeb sound and mode 7 for starters.

Let's see electon doing Rpi doom and stuntcar racer. Feck me it would be good to be able to run all games at correct speed/mode avail for elk, beeb and master in one machine and maybe even nula/co-pro Cpc and speccy emulation.

Ok i guess to take it that far with ultimate compatibility we would need a 6502 that has all the extra commands and abilities of all 3 systems to get all software for all working...

Still excited even to see it work even as a std Ula replacement
Last edited by mr-macrisc on Wed Jun 19, 2019 8:30 pm, edited 1 time in total.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Wed Jun 19, 2019 10:17 pm

mr-macrisc wrote:
Wed Jun 19, 2019 8:29 pm
Wasnt gonna post this but ah feck it... Why the hell cant i dream...
Quite a lot of this is possible; it all depends on what the software/RTL folks end up making once there are a few of these in the wild :)

The current design uses about 10% of the FPGA, so there's plenty of room there for things like coprocessors. It also doesn't use all that much of the SDRAM bandwidth (not to mention that there's 32MB of it), so bumping up the processor clock speed should be possible too.

Beeb/Master compatible ROM, Beeb sound, MODE 7 -- these are possible and pretty likely, although making the Electron keyboard work with the BBC MOS will probably require desoldering the 6502 and reimplementing it in the FPGA, or turning the 6502 into a simple IO processor just running a loop to poll the keyboard, moving all processing inside the ULA (although this would break compatibility with all other expansions).

AP5/+1/+3 -- these won't be in there, because they're all about external interfaces. This board is entirely internal unless you want to drill extra holes in your Electron, in which case there'll be a 3.3V serial port, a USB port, and stereo audio.

VideoNuLA -- will require an external conversion box because the R/G/B lines are buffered inside the Electron. I've made a little board that should let you plug the Elk directly into a VGA monitor, but it'll still only be able to do 8 colours. I'm sure someone will do something like this, but it'll be quite a bit of work.

My personal priorities are:

- Good storage: Fast access to an SD card, lots of ROMs in the flash chip, and bank-switchable sideways RAM. I want to be able to switch on my Elk with nothing attached to it and have it be usable; it should feel like a machine with a hard drive.

- Fully upgraded Elk: Remove RAM contention, 4MHz operation, shadow RAM. Basically do all the things that were possible BITD with hardware upgrades.

- External access with case open: USB serial port for BeebLink and flash programming (using the TinyFPGA bootloader)

- VGA output using my sync separator board
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Thu Jun 20, 2019 3:45 am

Progress so far... it didn't go up in smoke when run inside the Elk :D

It looks like it's doing something -- I can scope the clock and rom enable lines and they look about right. No screen display yet though; the CSYNC is looking good but nothing is showing on the red/green/blue lines.

The keyboard seems to be wired up OK; I have the caps LED blinking, and hitting break gives a reset pulse...
Last edited by myelin on Thu Jun 20, 2019 3:46 am, edited 1 time in total.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Thu Jun 20, 2019 6:12 am

Turning in for the night... have tried logging the boot process with fx2pipe and 6502Decoder, and suspect something is wrong with the ram, or maybe I need to tweak the timing on the data buffer enables. Will see what I can figure out from the logs tomorrow!
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Thu Jun 20, 2019 4:31 pm

Here’s a photo of the current setup:
A2C93477-2E63-41F5-8A79-CE5BE44DF29B.jpeg
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by Ramtop » Thu Jun 20, 2019 7:52 pm

We are eagerly waiting to see if the monster lives, Dr Frankenstein :D
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Thu Jun 20, 2019 10:14 pm

Ramtop wrote:
Thu Jun 20, 2019 7:52 pm
We are eagerly waiting to see if the monster lives, Dr Frankenstein :D
It's... somewhat alive? Using the FX2 and Hoglet's 6502decoder, I can see it proceeding as expected through the usual reset process, then kinda going off into the weeds while servicing the first interrupt (which happens way earlier than in a recording from another machine, so something is fishy there) --

Code: Select all

D95C : 58       : CLI            : 2 : A=07 X=00 Y=00 SP=A3 N=0 V=0 D=0 I=0 Z=0 C=1
D95D : 78       : SEI            : 2 : A=07 X=00 Y=00 SP=A3 N=0 V=0 D=0 I=1 Z=0 C=1
D95E :          : INTERRUPT !!   : 7 : A=07 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=0 C=1
DAE7 : 85 FC    : STA FC         : 3 : A=07 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=0 C=1
DAE9 : 68       : PLA            : 4 : A=25 X=00 Y=00 SP=A1 N=0 V=0 D=0 I=1 Z=0 C=1
DAEA : 48       : PHA            : 3 : A=25 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=0 C=1
DAEB : 29 10    : AND #10        : 2 : A=00 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=1 C=1
DAED : D0 17    : BNE DB06       : 2 : A=00 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=1 C=1
DAEF : 6C 04 02 : JMP (0204)     : 5 : A=00 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=1 C=1
4702 : DB       : ???            : 1 : A=00 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=1 C=1
4703 : D8       : CLD            : 2 : A=00 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=1 C=1
4704 : A5 FC    : LDA FC         : 3 : A=07 X=00 Y=00 SP=A0 N=0 V=0 D=0 I=1 Z=0 C=1
4706 : 48       : PHA            : 3 : A=07 X=00 Y=00 SP=9F N=0 V=0 D=0 I=1 Z=0 C=1
4707 : 8A       : TXA            : 2 : A=00 X=00 Y=00 SP=9F N=0 V=0 D=0 I=1 Z=1 C=1
4708 : 48       : PHA            : 3 : A=00 X=00 Y=00 SP=9E N=0 V=0 D=0 I=1 Z=1 C=1
4709 : 98       : TYA            : 2 : A=00 X=00 Y=00 SP=9E N=0 V=0 D=0 I=1 Z=1 C=1
470A : 48       : PHA            : 3 : A=00 X=00 Y=00 SP=9D N=0 V=0 D=0 I=1 Z=1 C=1
470B : A9 DB    : LDA #DB        : 2 : A=DB X=00 Y=00 SP=9D N=1 V=0 D=0 I=1 Z=0 C=1
470D : 48       : PHA            : 3 : A=DB X=00 Y=00 SP=9C N=1 V=0 D=0 I=1 Z=0 C=1
470E : A9 81    : LDA #81        : 2 : A=81 X=00 Y=00 SP=9C N=1 V=0 D=0 I=1 Z=0 C=1
4710 : 48       : PHA            : 3 : A=81 X=00 Y=00 SP=9B N=1 V=0 D=0 I=1 Z=0 C=1
4711 : AC 00 FE : LDY FE00       : 4 : A=81 X=00 Y=A0 SP=9B N=1 V=0 D=0 I=1 Z=0 C=1
4714 : 98       : TYA            : 2 : A=A0 X=00 Y=A0 SP=9B N=1 V=0 D=0 I=1 Z=0 C=1
4715 : 4A       : LSR A          : 2 : A=50 X=00 Y=A0 SP=9B N=0 V=0 D=0 I=1 Z=0 C=0
4716 : 90 13    : BCC 472B       : 3 : A=50 X=00 Y=A0 SP=9B N=0 V=0 D=0 I=1 Z=0 C=0
472B : A2 05    : LDX #05        : 2 : A=50 X=05 Y=A0 SP=9B N=0 V=0 D=0 I=1 Z=0 C=0
pc: prediction failed at DB71 old pc was 472D
DB71 : 20 A8 F0 : JSR F0A8       : 6 : A=50 X=05 Y=A0 SP=99 N=0 V=0 D=0 I=1 Z=0 C=0
F0A8 : A5 F4    : LDA F4         : 3 : A=00 X=05 Y=A0 SP=99 N=0 V=0 D=0 I=1 Z=1 C=0
F0AA : 48       : PHA            : 3 : A=00 X=05 Y=A0 SP=98 N=0 V=0 D=0 I=1 Z=1 C=0
F0AB : 8A       : TXA            : 2 : A=05 X=05 Y=A0 SP=98 N=0 V=0 D=0 I=1 Z=0 C=0
I suspect something is going wrong with memory timing, because it looks like the address read from &0204 wasn't logged correctly. The 6502 seems to have managed all right, because the instructions are correct for a jump to DB47, but I'm guessing the FX2 device did something like a double read on the 02 byte.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Fri Jun 21, 2019 5:28 am

*Facepalm*

Looks like the ULA internally pulls up /IRQ and /NMI, which is why they're both floating around 0V and causing my 6502 to behave strangely.

Time to go solder on some resistors :)
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Fri Jun 21, 2019 5:45 am

All right... two 10k resistors soldered on top of everything and now on reset I'm seeing a brief "Acorn Electron" banner, so something is working!

The FX2 only seems to be returning garbage, which is a bit puzzling, but there's definitely something happening now...
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Fri Jun 21, 2019 6:11 am

Anyone seen this before? I get “Acorn Electron”, a blank line, then the screen fills with @@@@@... and the banner scrolls off the top.

Also there must be something interesting about reset and the ULA’s clock generation; when I stop the clock during reset, it results in the FX2 missing the reset event and (I think) the 6502 missing it most of the time as well. Does the ULA do something clever and run the clock for a bit (but not the whole time) during reset?
4248D75E-4DF0-4BBA-A291-2B10B44BF16E.jpeg
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by hoglet » Fri Jun 21, 2019 6:14 am

myelin wrote:
Fri Jun 21, 2019 5:45 am
The FX2 only seems to be returning garbage, which is a bit puzzling, but there's definitely something happening now...
Are you capturing synchronously, on the falling clock edge, using fx2pipe?

Can you post a trace file?

What I found on the Master was I needed to delay Sync by a few nano seconds - adding a 2K2 resistor inline was sufficient.

I wonder if your @@@@@@ are the tube detection going wrong, and the MOS wrongly thinks there is a second processor present.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by hoglet » Fri Jun 21, 2019 6:23 am

If it were the tube detection code going wrong, FCE0 bit 0 would have to be toggle-able, in the same manner that it is in the tube control register:

Code: Select all

LDA #&81:STA LFCE0     :\ Write &81 to Tube control
LDA LFCE0              :\ Read back from Tube control
ROR A:BCC LDA16        :\ Bit 0 didn't remain set, no Tube
LDA #&01:STA LFCE0     :\ Write &01 to Tube control
LDA LFCE0              :\ Read back from Tube control
ROR A:BCS LDA16        :\ Bit 0 didn't remain clear, no Tube
http://mdfs.net/System/ROMs/AcornMOS/El ... ELK100.zip

Dave
Last edited by hoglet on Fri Jun 21, 2019 1:02 pm, edited 3 times in total.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Fri Jun 21, 2019 2:09 pm

I had no idea the Elk MOS had Tube detection at all!

I've attached a .bin file suitable for decoding with: ./decode6502 -s --machine=elk -h -y --phi2= --sync= --rdy= 2019-06-20-elkula-2.bin

Here's something interesting -- this machine seems to take one fewer cycle to start up after the rising RST edge, so 6502Decoder is one cycle off. It's a UM6502CE (4MHz part)... I'll try replacing with a 6502A and seeing if that changes anything.

Code: Select all

889028 18 rnw:1 sync:1 rdy:1 phi2:0 rst:0
889029 18 rnw:1 sync:1 rdy:1 phi2:0 rst:0
889030 18 rnw:1 sync:1 rdy:1 phi2:0 rst:0
889031 18 rnw:1 sync:1 rdy:1 phi2:0 rst:0
889032 18 rnw:1 sync:1 rdy:1 phi2:0 rst:1
889033 18 rnw:1 sync:1 rdy:1 phi2:0 rst:1
889034 18 rnw:1 sync:1 rdy:1 phi2:0 rst:1
-1 18 1 1
889035 da rnw:1 sync:1 rdy:1 phi2:0 rst:1
0 18 1 1
889036 be rnw:1 sync:1 rdy:1 phi2:0 rst:1
1 18 1 1
889037 dc rnw:1 sync:1 rdy:1 phi2:0 rst:1
2 da 1 1
889038 d2 rnw:1 sync:1 rdy:1 phi2:0 rst:1
3 be 1 1
889039 d8 rnw:1 sync:1 rdy:1 phi2:0 rst:1
4 dc 1 1
889040 a9 rnw:1 sync:1 rdy:1 phi2:0 rst:1
5 d2 1 1
889041 40 rnw:1 sync:1 rdy:1 phi2:0 rst:1
6 d8 1 1
889042 8d rnw:1 sync:1 rdy:1 phi2:0 rst:1
7 a9 1 1
889043 00 rnw:1 sync:1 rdy:1 phi2:0 rst:1
E3A9 :          : RESET !!       : 11 : A=83 X=0E Y=0F SP=?? N=1 V=? D=? I=1 Z=0 C=1
0 40 1 1
889044 0d rnw:1 sync:1 rdy:1 phi2:0 rst:1
1 8d 1 1
889045 40 rnw:0 sync:1 rdy:1 phi2:0 rst:1
2 00 1 1
889046 78 rnw:1 sync:1 rdy:1 phi2:0 rst:1
3 0d 1 1
889047 d8 rnw:1 sync:1 rdy:1 phi2:0 rst:1
4 40 0 1
889048 d8 rnw:1 sync:1 rdy:1 phi2:0 rst:1
5 78 1 1
889049 a2 rnw:1 sync:1 rdy:1 phi2:0 rst:1
A9D8 : 40       : RTI            : 6 : A=83 X=0E Y=0F SP=?? N=0 V=0 D=0 I=0 Z=0 C=0
0 d8 1 1
889050 a2 rnw:1 sync:1 rdy:1 phi2:0 rst:1
1 d8 1 1
889051 ff rnw:1 sync:1 rdy:1 phi2:0 rst:1
780D : D8       : CLD            : 2 : A=83 X=0E Y=0F SP=?? N=0 V=0 D=0 I=0 Z=0 C=0
0 a2 1 1
889052 9a rnw:1 sync:1 rdy:1 phi2:0 rst:1
1 a2 1 1
889053 e8 rnw:1 sync:1 rdy:1 phi2:0 rst:1
780E : A2 A2    : LDX #A2        : 2 : A=83 X=A2 Y=0F SP=?? N=1 V=0 D=0 I=0 Z=0 C=0
0 ff 1 1
889054 e8 rnw:1 sync:1 rdy:1 phi2:0 rst:1
7810 : FF       : ???            : 1 : A=83 X=A2 Y=0F SP=?? N=1 V=0 D=0 I=0 Z=0 C=0
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Last edited by myelin on Fri Jun 21, 2019 2:11 pm, edited 1 time in total.
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by hoglet » Fri Jun 21, 2019 2:29 pm

myelin wrote:
Fri Jun 21, 2019 2:09 pm
Here's something interesting -- this machine seems to take one fewer cycle to start up after the rising RST edge, so 6502Decoder is one cycle off. It's a UM6502CE (4MHz part)... I'll try replacing with a 6502A and seeing if that changes anything.
Try adding the -c option.

This switches to the 65C02 model, which (for some reason) seems to better match the UM6502CE you have.

With this, you get a clean decoder trace.

Dave
Last edited by hoglet on Fri Jun 21, 2019 2:30 pm, edited 1 time in total.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by hoglet » Fri Jun 21, 2019 2:39 pm

If I compare your trace to a known good Elk, the first significant divergence is here at line 13:

Your trace:

Code: Select all

D8DD : 8E 00 FE : STX FE00       : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8E0 : 8E 8D 02 : STX 028D       : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8E3 : A9 F8    : LDA #F8        : A=F8 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8E5 : 8D 05 FE : STA FE05       : A=F8 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8E8 : AD 00 FE : LDA FE00       : A=A0 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8EB : 29 02    : AND #02        : A=00 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
My trace:

Code: Select all

D8DD : 8E 00 FE : STX FE00       : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8E0 : 8E 8D 02 : STX 028D       : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8E3 : A9 F8    : LDA #F8        : A=F8 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8E5 : 8D 05 FE : STA FE05       : A=F8 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8E8 : AD 00 FE : LDA FE00       : A=B2 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8EB : 29 02    : AND #02        : A=02 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=0 C=?
The value of A differs at the end of this sequence.

This is probably resting for a power up reset.

Was your trace of a power up reset?

Dave
Last edited by hoglet on Fri Jun 21, 2019 2:40 pm, edited 1 time in total.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by myelin » Fri Jun 21, 2019 2:43 pm

Nope, not a power up reset... I'll see if I can get a recording like that (holding break while applying power, reset the FPGA, run fx2pipe, release break).

For now here's another recording, after swapping the UM6502CE out for a SY6502A. Looks a lot more like a recording from another Elk, when I was debugging my Plus 1 a year ago. See anything interesting in there? Notes for this recording:

- SY6502A CPU
- warm boot (held BREAK, ran fx2pipe, released BREAK)
- "Acorn Electron" banner showed, then scrolled off the top of the screen
- No @@@@ or anything; just a blank screen once the banner had scrolled off the top
Attachments
2019-06-20-elkula-startup-sy6502a.zip
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Re: Proposed: "The Ultimate Electron Upgrade"

Post by -B- » Fri Jun 21, 2019 2:48 pm

Wow! I haven't checked this thread in a while but I see you've been busy! =D>
Atom | BBC Model A | BBC Model B | Electron | Olivetti PC128S.

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Re: Proposed: "The Ultimate Electron Upgrade"

Post by hoglet » Fri Jun 21, 2019 2:58 pm

It looks like the @@@@ characters were the title string of ROM 15 being printed.

What ROM image is in slot 15?

(It was an infinite sequence because there was no null terminator.)

So possibly the ROM detection code is failing, and thinking there is a ROM present when there isn't?

Feels like we are close.....

Dave
Last edited by hoglet on Fri Jun 21, 2019 3:27 pm, edited 2 times in total.

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