Tube ULA Reverse Engineering

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quaffle51
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Re: Tube ULA Reverse Engineering

Post by quaffle51 » Wed Jul 04, 2018 8:20 am

At this time I'm only interested in the TUBE ula. It was while looking at the CoProc6502 FPGA verilog code that I started to wonder where the original information had come from that enabled such a detailed design of the TUBE functionality in verilog. (Also, how others had done so too as there are a few closed source design for the TUBE out there as listed at the start of this thread). At the same time I had been doing a MOOC called NAND2Tetris https://www.nand2tetris.org/ which shows the development of a basic computer built up from NAND gates. The TUBE ula seems to be built up from NOR gates. So then it became obvious to me that all the information needed to specify the functionality of the TUBE was in the original image of the TUBE ula provided to you by Steve. Then I read an article on the BBC News site https://www.bbc.com/news/technology-44525358 which detected illegal images on a picture sharing site and wondered if I could apply the same technique to identify digial objects like NOR gates, inverters, D type Flip-Flops etc in the original TUBE image. But the missing link as it were would be how to automatically detect how these digital objects are connected together, Hence, my request to see if the original TUBE image was in the public domain and to follow your workflow to see how you had achieved this. If I achieve anything from this work I will of course publish it here.
Last edited by quaffle51 on Wed Jul 04, 2018 8:26 am, edited 2 times in total.

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hoglet
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Re: Tube ULA Reverse Engineering

Post by hoglet » Wed Jul 04, 2018 9:39 am

quaffle51 wrote:
Wed Jul 04, 2018 8:20 am
At this time I'm only interested in the TUBE ula. It was while looking at the CoProc6502 FPGA verilog code that I started to wonder where the original information had come from that enabled such a detailed design of the TUBE functionality in verilog.
Actually, the Tube design we are using in the Matchbox Co Pro predates the reverse engineering effort by almost 5 years!

It was started by BigEd and Revaldinho back in 2008 in the context of the Beeb816 project.
https://sites.google.com/site/beeb816/h ... be-on-fpga

Much of how the Tube works was well documented by Acorn in:
http://chrisacorns.computinghistory.org ... AN/004.pdf

Maybe Ed or Richard will comment if they had other sources?

With their permission, I was able to re-use that code in the Matchbox Co Pro.

We've made a few changes/bug fixes along the way. The main design change relates to the synchronization primitive used in the FIFO flags. The original Beeb816 Tube implementation made extensive use of RS Flip Flops, which was fine as the Spartan 3 FPGA in the GODIL used by Beeb816 supports these natively. Unfortunately, the Spartan 6 on the Matchbox Co Pro doesn't, so we changed the approach to make use of properly request/acknowledge handshake signals.
quaffle51 wrote:
Wed Jul 04, 2018 8:20 am
The TUBE ula seems to be built up from NOR gates. So then it became obvious to me that all the information needed to specify the functionality of the TUBE was in the original image of the TUBE ula provided to you by Steve. Then I read an article on the BBC News site https://www.bbc.com/news/technology-44525358 which detected illegal images on a picture sharing site and wondered if I could apply the same technique to identify digial objects like NOR gates, inverters, D type Flip-Flops etc in the original TUBE image. But the missing link as it were would be how to automatically detect how these digital objects are connected together, Hence, my request to see if the original TUBE image was in the public domain and to follow your workflow to see how you had achieved this. If I achieve anything from this work I will of course publish it here.
I don't know if you realise, but the Java "ULA Mangling" code also extracts these high level objects. Specifically it:
- extracts transistors and the interconnection
- transforms the transistor level netlist into a gate level netlist (N input NOR Gates)
- identifies sets of NOR gates that form SR latches
- identifies pairs of SR latches that form D-type latches

Here's an example of the resulting netlist:
https://github.com/hoglet67/TubeULA/blo ... tchlevel.v

This we were able to successfully simulate.

In terms of actually understanding the design, there is still along way to go. Steve Furber (the designer) has a research interest in self-timed asynchronous logic. The TubeULA makes use of this implementation technique. Unfortunately, that means it is not directly transferable to a modern FPGA, since (for various reasons) it's not possible to use this design style reliably in an FPGA.

Hence, when we came to implement the Tube ULA in the Matchbox Co Pro, we chose to base this on the earlier Beeb816 work, rather than trying to directly use the results of the reverse engineering effort.

Where the reverse engineering has proved useful is being able to run simulations to verify certain aspects of the Tube's behaviour. For example, there was some confusion over exactly how the N flag worked, and simulation plus looking at the gate level netlist cleared this up.

By the way, I know of several other independent Tube re-implementations:
- John Kortink has an implementation used in ReTuLa, and in his other Co Processors (closed source).
- Mark Haysman has an implementation used in his Retroclinic SuperCo 6502i Co Processor (closed source).
- Robert Sprowson has an implementation used in his ARM7TDMI Co Processor (closed source).
- Stephen Leary (@terriblefire) has an implementation that I don't believe has been published (he gave me a copy in 2016).

So as far as I know, the Beeb816 and Matchbox derivative is still the only open source implemetation.

I hope this gives you a bit more context.

Dave
Last edited by hoglet on Wed Jul 04, 2018 9:52 am, edited 1 time in total.

quaffle51
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Re: Tube ULA Reverse Engineering

Post by quaffle51 » Wed Jul 04, 2018 12:01 pm

Dave, many thanks for this update which does indeed put things in context some of which I was not aware of. I certainly do not want to "reinvent the wheel", but I am keen work through your workflow as I'm sure I can learn from your work. To this end, I'm most grateful for the information you have given which will enable me to make a start.

Gordon.

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BigEd
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Re: Tube ULA Reverse Engineering

Post by BigEd » Wed Jul 04, 2018 12:31 pm

IIRC, the only other source of Tube info that we had back in 2009/10 was Yellow Pig's site:
http://www.cowsarenotpurple.co.uk/bbcco ... /tube.html

(Looks like we started musing about a Tube remake in March or April 2009, and published in 2010. This thread was a very early hint about feasibility. We'd found JGH's mdfs.net by this time. We also noted a $159 100MHz ARM board suitable for a 40 pin socket, and noted the propeller chip, for possible emulation, also XMOS' XCore offerings, but we had no concrete ideas at that time and we didn't follow up. Our first CPLD experience was in June 2009, and we were trying to converge on a single multi-purpose PCB which could act as in-socket accelerator, tube-connected second processor, standalone single board computer, or CPLD playground. But we knew our CPLD was too small to fit a full Tube. By October we'd discovered OHO's GODIL boards and were thinking of an FPGA Tube. It was December before our PCB design was final and in fab. It was April 2010 before Rich's first Tube-like verilog. Edit: and first life on 12th May.)

Edits: linkification
Last edited by BigEd on Wed Jul 04, 2018 6:27 pm, edited 3 times in total.

dominicbeesley
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Re: Tube ULA Reverse Engineering

Post by dominicbeesley » Thu Jul 05, 2018 10:57 am

hoglet wrote:
Wed Jul 04, 2018 9:39 am

So as far as I know, the Beeb816 and Matchbox derivative is still the only open source implemetation.
I did a simplistic VHDL effort with an eye on BigEd's work for my 65816 experiments a few years ago (2015). I didn't try and make it 100% compatible just good enough to get the thing to work with BASIC etc. viewtopic.php?f=3&t=13559&p=177599#p177592

I'm happy to spend some time adding and Open Source licence and sticking it on Github if there's any interest

I'm also very interested in any reverse engineered version!

D

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BigEd
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Re: Tube ULA Reverse Engineering

Post by BigEd » Thu Jul 05, 2018 12:00 pm

It'd be great to have another open source implementation!

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Re: Tube ULA Reverse Engineering

Post by puppeh » Tue Jul 10, 2018 7:54 pm

I had a go at implementing the Tube once! But my attempt wasn't even tested in the end, so is of no practical use to anyone.

I'd got a pile of chips (a 65816, some logic chips to act as glue, and a Xess FPGA board) with the intention of hooking the '816 up to a beeb via the Tube - but I struggled to make it work reliably even not connected to the beeb, and the FPGA board only had SDRAM on it, and talking to SDRAM as a first Verilog project Isn't Very Easy. Even with someone else's SDRAM controller code. So that was more-or-less that!

The code's at https://github.com/puppeh/fpgateletext/ ... ter/tube.v. Feel free to steal if there's any possibility it's vaguely helpful.

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Re: Tube ULA Reverse Engineering

Post by dominicbeesley » Mon Jul 16, 2018 3:17 pm

BigEd wrote:
Thu Jul 05, 2018 12:00 pm
It'd be great to have another open source implementation!
Here you go, I've added an Unlicence so if there's anything of any use feel free to help yourselves! I've not got much time to make it pretty but it should all be there https://github.com/dominicbeesley/65816_tube_altera

I really should pull my finger out make this into something a bit more reproducible...or even better make a 65816 FPGA core!

D

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BigEd
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Re: Tube ULA Reverse Engineering

Post by BigEd » Mon Jul 16, 2018 3:43 pm

Thanks!

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