: For my HD floppies mod, I've clocked 1772's at 16MHz when they're spec'd (on paper at least) to 10MHz but I guess that's an unexpected advanage of these older chips - they're made of pig-iron and seem to be virtually unburstable
: Read on...
On the address issue, I was going to briefly explain for novices how that works so...
The primary control of digital chips such as SID often boils down to just one signal which is typically the /CS line. The '/' is written to represent a bar above the signal mnemonic (as in my schematic) and means the chip will wake-up and talk or listen when the line goes low. Thus, to locate BeebSID at $FCE0, I use a 74LS30 which is an eight input NAND gate and this chip will set it's output line low (which is connected to SID's /CS) when all it's eight inputs are high. All 1MHz bus devices need to respond when NPGFC is low (like '/', the N here means NOT or low) and at the same time as the 1MHzE clock is high. Thus, I use the cleaned and inverted-to-high NPGFC and the 1MHzE signal as two of the eight inputs to the LS30. The NPGFC signal has done the $FCxx part of the decode for me so I then just use address lines A5, A6 & A7 to select the $xxEx (or $xxFx) portion of the address. By connecting these directly to another three inputs of the LS30, I will only get a /CS whenever all these are high together, i.e. at $FCEx or $FCFx. The remaining five address lines A0-A5 go directly to SID and give us 32 possible combinations or mapped locations which equate to the SID's 29 (3 not used) registers. The three spare inputs to the LS30 are tied high (connected to +5v) and are thus always 'true'.
The /CS signal is then used by SID as a prompt to talk when the R/W line is high and to listen when the R/W is low. The 02 clock line keeps everything in sync and SID probably (?) uses a divided version of it for it's tone oscillator.
Now, returning to the thorny issue of FRED addresses...
It looks as if it is going to be nigh on impossible to find 29 contiguous locations without trampling on something because it seems that Electron has snaffled a few entries at the start of each nibble boundary ($xxx0) within FRED and this, combined with all the Beeb stuff has left lots of spaces but none as big as SID needs. I haven't given lots of thought to the Elk as yet but it's always in my mind and I definitely don't want to rule it out by clashing with any of it's potential hardware expansions.
* Thus, after careful consideration, I have decided to formally declare that BeebSID will reside at $FC20 to $FC3C *
According to JGH's table, this area will theoretically only clash with the IEEE Adaptor, the Electron Econet interface and the Cambridge Ring interface. Now, since I don't know what any of those are, there can't possibly be a problem
That decided, lets look at how to change the current SID circuit to move the base address to $FC20.
As described already, the LS30 (SID's /CS driver) needs all it's inputs high to set it's output active low. The $FCxx is pre-selected by NPGFC, A4-A0 are connected directly to SID to select the 29 registers and we therefore ideally just want to use the remaining three addtess lines, A7-A5, to set our base address. $FC20 = $FC + % 0010 0000 and so we can see that A7-A5 will be %001 when we want to talk to SID. Since the LS30 requires all input lines to be high, if we simply invert A7 and A6 we will have what we need.
To achieve this we will add one more IC which will be a 74LS04. This is a Hex Inverter and contains six single input/output gates which do exactly what you would expect - they invert! We will use two of these gates and insert one in the A7 line between the one-meg bus connector Pin 34 & IC2 Pin 5 and a second in the A6 line between the one-meg bus connector Pin 33 & IC2 Pin 4. This done, SID has it's shiny new address at $FC20
The LS04 has six gates and we've only used two so we can additionally use the other four in two pairs (forming double inverters) as buffers for the well-used 1MHzE and for the always overburdened R/W (Read/Write) line. (Note that any gate does add a few nano-seconds delay to a signal so it's not always possible to throw in gates at will because subtle timing issues can arise.)
I'll now try and update the drawing in some way or if that proves too difficult I'll have to start again
(Unless of course there any willing and able electronic layout specialists out there....
(I feel really punch-drunk now because doing is much simpler than explaining and there may be typos in there - please don't hesitate to shout up if something sounds or looks wrong )