BigEd wrote: ↑
Sun Aug 16, 2020 2:15 pm
BigEd wrote: ↑
Sat Aug 15, 2020 9:59 pm
So, are we feeding in a higher Vreg, so that Vs is elevated relative to normal? In other words, VIDPROC is an overvoltaged ULA.
Hmm, on more careful reading, it seems it might be the other way around: we are feeding in a lower Vreg. I'm feeling confused now!
Both the Ferranti Video ULA in the Beeb and the Ferranti ULA used in the ZX Spectrum use a +5V supply for the peripheral cells so that the I/O pins can Interface to 5V TTL level logic systems.
They also both use a separate lower voltage supply (pin 15 in the case of the Video ULA, pin 13 in the case of the ZX Spectrum ULA) to supply the on chip series pass element voltage regulators which produce a 0.84V and 0.95V supply that in turn feeds the CML circuitry that forms the matrix cells.
Doing it this way reduces the amount of power that the chip series pass element voltage regulators have to dissipate, and hence reduce the temperature of the chip overall.
The peripheral cells can be configured as desired to interface with the expected input signal(s). And the peripheral cells can be configured as desired to output a choice of output types (including open connector, push-pull and tri-state). Both obviously have to be designed within the limitations of the available ‘building blocks’.
So the 16MHz clock input may or may not be a TTL type input... Without looking at either a chip schematic or looking at the interconnect layer of a decapped chip, we can only guess.