VIDPROC V2 (pin 15) - please explain!

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Richard Russell
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Re: VIDPROC V2 (pin 15) - please explain!

Post by Richard Russell » Sun Aug 16, 2020 3:48 pm

Coeus wrote:
Sun Aug 16, 2020 3:28 pm
Do we know what the output impedance is?
The output impedance of TTL (or STTL) is very asymmetrical, much lower in the logic 0 state than at logic 1, and I doubt that 50Ω is a good approximation to either.
has someone applied the old 10X rule?
I don't think such a 'rule' would be applicable here. On my Transform PAL Decoder, when it's a 35.5 MHz clock that I'm distributing, the sending end is two paralleled 74VHC125 outputs and the termination is a 150Ω resistor in series with a 10nF capacitor.

dp11
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Re: VIDPROC V2 (pin 15) - please explain!

Post by dp11 » Sun Aug 23, 2020 12:34 pm

Some scope traces form an Issue7 mother board with VTI ULA

IC40 Pin13
Pin13.png
IC40 Pin12
Pin12.png
IC40 Pin11
Pin11.png

ULA Pin8
ULAPin8.png
ULA Pin15
ULAPin15.png

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1024MAK
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Re: VIDPROC V2 (pin 15) - please explain!

Post by 1024MAK » Mon Aug 24, 2020 3:27 pm

BigEd wrote:
Sun Aug 16, 2020 2:15 pm
BigEd wrote:
Sat Aug 15, 2020 9:59 pm
So, are we feeding in a higher Vreg, so that Vs is elevated relative to normal? In other words, VIDPROC is an overvoltaged ULA.
Hmm, on more careful reading, it seems it might be the other way around: we are feeding in a lower Vreg. I'm feeling confused now!
Both the Ferranti Video ULA in the Beeb and the Ferranti ULA used in the ZX Spectrum use a +5V supply for the peripheral cells so that the I/O pins can Interface to 5V TTL level logic systems.

They also both use a separate lower voltage supply (pin 15 in the case of the Video ULA, pin 13 in the case of the ZX Spectrum ULA) to supply the on chip series pass element voltage regulators which produce a 0.84V and 0.95V supply that in turn feeds the CML circuitry that forms the matrix cells.

Doing it this way reduces the amount of power that the chip series pass element voltage regulators have to dissipate, and hence reduce the temperature of the chip overall.

The peripheral cells can be configured as desired to interface with the expected input signal(s). And the peripheral cells can be configured as desired to output a choice of output types (including open connector, push-pull and tri-state). Both obviously have to be designed within the limitations of the available ‘building blocks’.

So the 16MHz clock input may or may not be a TTL type input... Without looking at either a chip schematic or looking at the interconnect layer of a decapped chip, we can only guess.

Mark

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Re: VIDPROC V2 (pin 15) - please explain!

Post by 1024MAK » Mon Aug 24, 2020 3:35 pm

One further point that is worth taking into account, the Ferranti ULA will draw a reasonable amount of current through resistor R114. Hence the voltage at the junction of R114 and diode D16 may not be fully dependent on the forward voltage drop of diodes D16, D17 and D18.

However, if a VTI Videoproc chip is used, does this actually use the lower voltage supply on socket pin 15? If no, then the voltage here (at the junction of R114 and diode D16) will be purely determined by the forward voltage drop of diodes D16, D17 and D18.

Mark

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