VIDPROC V2 (pin 15) - please explain!

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BigEd
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VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 11:00 am

I find the circuit around pin 15 of the Video ULA very odd - can anyone help me to understand it informally? I see three resistors, three diodes, and a capacitor, somehow modifying a 16 MHz clock.
IC6-VID-PROC-pt2.png
IC6-VID-PROC-pt2.png (133.99 KiB) Viewed 858 times
IC6-VID-PROC-pt1.png

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Re: VIDPROC V2 (pin 15) - please explain!

Post by dp11 » Sat Aug 15, 2020 11:18 am

The three diodes set an approx 1.8v rail for internal logic. The X is just biasing the 16Mhz clock.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 11:42 am

Ah, I'd very much missed the 0V annotation between the diodes and the capacitor! Thanks. That makes some sense to me now, constructing a 1.8V rail for internal use - we know the ULA initially had trouble related to noise and supply voltage. (All ULAs have a low voltage for the interior logic, but usually that's derived internally from the single supply rail.)

But... what's this about biasing the 16MHz clock? What high and low voltages would you expect, then, on the pin 8 clock input? And why might this be a good idea? (And this means the arrows on the connection 'X' are pointing the wrong way, I think. If so, that could perhaps be a useful correction in the schematic thread.)

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Coeus » Sat Aug 15, 2020 1:01 pm

BigEd wrote:
Sat Aug 15, 2020 11:42 am
But... what's this about biasing the 16MHz clock? What high and low voltages would you expect, then, on the pin 8 clock input? And why might this be a good idea? (And this means the arrows on the connection 'X' are pointing the wrong way, I think. If so, that could perhaps be a useful correction in the schematic thread.)
Surely it depends on the internal resistance of the output driver of the 74S00? If the 74S00 was disconnected then voltage at pin 8 would half that at point X so 0.9V. If the 74S00 had zero internal resistance then the voltage on pin 8 would be whatever it was driving it to. Reality is presumably between the two. Does the datasheet for a 74S00 give this output impedance?

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 1:37 pm

The wibbly-wobbly datasheet for the TI part says this:

[oops wrong table - see downthread)
TI-SN74S00-circuit.png
Last edited by BigEd on Sat Aug 15, 2020 3:39 pm, edited 2 times in total.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Coeus » Sat Aug 15, 2020 2:17 pm

Ed, that's for a 74LS00 the circuit diagram has an 74S00 without the L.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 2:24 pm

Pretty sure not: it's a multi-purpose datasheet for the '00, the L, the LS, the H, and the S - I believe I pasted the bits marked as being for the S.

Oops, but no, I see you're right: I got the right diagram but the wrong table.
Let me try again.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 2:26 pm

Second go:
TI-SN74S00-table-2.png

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Coeus » Sat Aug 15, 2020 3:08 pm

Ok, I am not sure what the proper way of solving this but let's have a hypothesis that the output of the 7S00 is 3.4V, i.e. high. That would mean there would be 1.6V across R107 so the current through R107 would be 1.6mA. There would be 3.4V across R98 so the current through that would be 3.4mA. Total output current is 5mA which is in within the output capability of the 74S00 so I that's exactly what you;d expect to see, unless there is significant loading from somewhere else? Where does the arrow 16Mhz go?

What about a low output of 0 to 0.5V? R107 would have at most 1.8V across is so current would be 1.8mA. If the output is really 0V all the current from R107 will go into the output pin of the 74S00 and 1.8mA is well within capability. But again, is something else loading this?

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 3:36 pm

The 16MHz signal, as far as I can tell, goes nowhere, or somewhere (two LS393s), depending on the disk interface fitting and a jumper:
BBC-Micro-16MHz.png
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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 3:39 pm

(I'm using the PDF schematic posted here.)

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Re: VIDPROC V2 (pin 15) - please explain!

Post by dp11 » Sat Aug 15, 2020 3:44 pm

please note the high of 3.4v is only at a load of 1mA DC for the S00

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 4:27 pm

If it weren't for the use elsewhere of this 16MHz signal, which surely requires that it works as a clock on the input of an LS device, I would wonder if there's something special about this ULA input. It might be, perhaps, that 16MHz is at the limit of the ULA input response, and a bit of help getting it over and under the relevant thresholds is needed.

It might even be that if the circuit was drawn differently I'd be better able to see what it's doing!

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Kazzie » Sat Aug 15, 2020 5:07 pm

BigEd wrote:
Sat Aug 15, 2020 3:36 pm
The 16MHz signal, as far as I can tell, goes nowhere, or somewhere (two LS393s), depending on the disk interface fitting and a jumper:
BBC-Micro-16MHz.png
S27 is only set to the 16MHz clock for using an 8 inch floppy drive, per section 4.6 of the Service Manual. Given the responses to a thread last year, virtually nobody here has a Beeb configured that way.
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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 5:26 pm

Ah, interesting. So, it's quite possible that this extra biasing circuit is a late change to the Beeb, to make the VIDPROC work reliably, and was never tested with the 16MHz being needed by the disk circuitry. It's possible that what remains of the 16MHz input signal is not TTL compatible, but is what's needed for the ULA.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Coeus » Sat Aug 15, 2020 5:28 pm

So what technology is the VIDPROC? Is it still NMOS or did they switch to CMOS to keep the heat down given that the ULA version ran hot?

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 6:33 pm

The original Ferranti ULAs are a bipolar technology, not an MOS. And not TTL either!

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Kazzie » Sat Aug 15, 2020 9:06 pm

Now that I'm home, I can access my library, and my copy of Chris Smith's "The ZX Spectrum ULA". Early Spectrums also used the 5C000 series ULA, and he has a thorough explanation of the entire ULA family, as well as how it is used in the Spectrum. The ULAs are based on CML (current-mode logic) arrays, which use the presence or absence of current flow to represent logical values. Because of this, they have a much lower minimum supply voltage: 0.6 to 0.95 volts.

As an uncommitted Logic Array, the ULA contains several CML-based matrix cells that can be customised to suit the user. There are also peripheral cells that interface with the higher-voltage logic signals on the chip's pins.

From Chapter 5:
Peripheral cells operated from from Vcc whereas matrix cells operated from Vs which, in the case of CML arrays, was a regulated noise-free supply of between 0.84V and 0.95V generated by temperature compensated series-regulators located at the base of each peripheral cell. These regulators drove the Vs rail from Vreg (usually Vcc), and were controlled by a Bandgap reference voltage of between 1.35V and 1.5V provided by discrete componentes at two opposing corners of the chip. Since there are many Vs regulators evenly distributed around the outside of the array, the total current available was much greater than a single regulator could provide. Furthermore, as the number of cells in the matrix increased, so did the circumference of the array. This allowed more peripheral cells and series regulators to be fabricated, which in turn provided the additional current required by the increase in matrix cells.

All arrays could be powered from a single supply, where the internal VCC and regulator supply Vreg were commoned. Alternatively, CML arrays permitted the use of two separate supply voltages for Vcc and Vreg, producing a lower power dissipation without compromising speed
Given how hot the original VIDPROCs run, one can see why they use two supply voltages; one dreads to think how melty they'd be if they were commoned!

The Spectrum's ULA uses a 14MHz oscillator driven by an external crystal, which is then divided internally by a flip-flop to create a 7MHz global clock. From Chapter 10:
By driving the ULA with a master clock at twice the required frequency and dividing internally to 7MHz, Altwasser [the designer] achieved an accurate and stable clock at the required matrix cell voltage of Vs
A diagram shows this was achieved by applying the 14MHz clock to the base of a transistor, which repeatedly grounded a voltage divider (fed by Vs at the opposite end), to generate a Vs-based clock pulse for a D-type flip-flop.
IMG_20200815_2048264.jpg
The Beeb uses flip-flops in its ULA to generate the 8-1MHz clocks, but also requires the logic in the ULA to operate at 16MHz, so couldn't use a flip-flop to generate this clean Vs clock. (I believe that 32MHz operation was well beyond the capabilities of the C series of ULA, diagrams in Chris' book implies it would have topped out around 20Mz. The R series could go faster, but they were only introduced at the end of 1981, so too late for the launch of the Beeb.)

Given that the matrix cells will want a clock signal that with a peak value of Vs, it would make sense for the 16MHz clock input to be biased halfway between 0V and Vs (or X) by the pair of 1K resistors R98 and R107, before being input into the ULA. Having said that, I might have expected to see a coupling capacitor on the output of IC40 pin 11 if that were the case, and my experience is that the DC voltage at pin 8 is nearer to 1.6V. I can only imagine that this is of some benefit to the peripheral cells that convey the clock signal into the matrix.

Perhaps someone else can take a stab at how the peripheral cells would be organised to convey and distribute a Vs 16MHz clock to the matrix cells? Here are the uncommitted elements that you'd have in each cell to work with:
IMG_20200815_2053227.jpg
  • Two coupled tranistors rated at 5mA and 16mA
  • One transistor rated at 16mA
  • One transistor rated at 5mA
  • Two general purpose transistors
  • A 16K pull-up resistor
  • Six resistors of value 200R, 1K, 2K, 3K, 5K and 5K
  • One voltage divider of 4K and 400R
  • A Vs supply rail at 0.84 or 095V, depending on ULA type
  • A Vcc supply rail at between 3.5 and 5.5V
  • A reference voltage rail
  • A ground rail
  • Three cross-unders (to the matrix cells)
  • An IC pin bond pad
Here's a similar diagram for a matrix cell:
IMG_20200815_2052532.jpg
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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sat Aug 15, 2020 9:59 pm

So, are we feeding in a higher Vreg, so that Vs is elevated relative to normal? In other words, VIDPROC is an overvoltaged ULA. Interesting.

Still would be interesting to understand the clock better. One reason for dividing a clock by two, as the Spectrum does, is to produce a symmetrical clock. It might be that the biasing is to push a slightly asymmetric clock's edges up (or down) to get closer to 50/50. (Or further away, depending on the clocking inside the ULA...)

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Kazzie » Sun Aug 16, 2020 7:13 am

BigEd wrote:
Sat Aug 15, 2020 9:59 pm
So, are we feeding in a higher Vreg, so that Vs is elevated relative to normal? In other words, VIDPROC is an overvoltaged ULA. Interesting.
I'm not absolutely sure of that, given that the default setup was to have Vreg at Vcc. It is certainly above the minimum, though. Perhaps there was a tradeoff between power dissipation and transition times (speed)?
BigEd wrote:
Sat Aug 15, 2020 9:59 pm
Still would be interesting to understand the clock better. One reason for dividing a clock by two, as the Spectrum does, is to produce a symmetrical clock. It might be that the biasing is to push a slightly asymmetric clock's edges up (or down) to get closer to 50/50. (Or further away, depending on the clocking inside the ULA...)
In light of that, it may be worth reconsidering the role of IC40 and its RC network. There must be a reason Acorn didn't just use the output of IC43 pin 6 instead...
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Re: VIDPROC V2 (pin 15) - please explain!

Post by Richard Russell » Sun Aug 16, 2020 10:21 am

I'm wondering if the two 1K resistors (R98 and R107) could be a termination on the end of a long run of track carrying the 16 MHz clock. It is notoriously difficult to distribute high-frequency clocks around a PCB for any distance without reflections causing over/undershoots and potentially multiple edges. If one looks at the pair of resistors as a 500 ohm termination to a voltage roughly half way between a logic 0 and 1 it makes sense.

If that is the explanation it would imply that the track carrying the clock is behaving as a transmission line with about 500 ohms characteristic impedance, which sounds on the high side to me (considered as a microstrip it would have to be very narrow). So maybe I'm wide of the mark, but the resistors aren't likely to be having any significant effect on DC logic levels (the output of the S00 is too low impedance, even in the logic 1 state, for that to be the case) so a high-frequency function seems more plausible.

If I'm right the topology of the board would be the giveaway (the resistors would be at the opposite end of the 16 MHz track from the driving gate).

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Re: VIDPROC V2 (pin 15) - please explain!

Post by cmorley » Sun Aug 16, 2020 11:13 am

RR is probably on the money here about termination. R98 is close to the ULA pin (5mm) & S27 is close by East of the ULA. R107 isn't far located next to the C47 cap for the V2 supply. The run from IC40 isn't far (70mm as the crow flies, maybe 100mm trace) but there is no ground plane on the PCB.

So termination seems likely.

Careful scoping at the ULA with R98 & R107 fitted then removed might be interesting to see.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by dp11 » Sun Aug 16, 2020 2:11 pm

Usually if the impedance is greater than the impedance if free space( 377Ohms ) Termination becomes hard .

I agree careful scoping would help.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sun Aug 16, 2020 2:15 pm

BigEd wrote:
Sat Aug 15, 2020 9:59 pm
So, are we feeding in a higher Vreg, so that Vs is elevated relative to normal? In other words, VIDPROC is an overvoltaged ULA.
Hmm, on more careful reading, it seems it might be the other way around: we are feeding in a lower Vreg. I'm feeling confused now!

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Richard Russell » Sun Aug 16, 2020 2:22 pm

dp11 wrote:
Sun Aug 16, 2020 2:11 pm
Usually if the impedance is greater than the impedance if free space( 377Ohms ) Termination becomes hard .
If it is a termination, I doubt that the impedance will have been determined 'scientifically'; it's more likely that Acorn will have tried a few resistor values to see which had the desired effect. Even if not eliminating reflections as such, it could be damping over/undershoots. It still seems to me that, whatever the purpose, it's more likely to be a high-frequency effect than anything that could be explained by changing DC logic levels.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Richard Russell » Sun Aug 16, 2020 2:30 pm

BigEd wrote:
Sun Aug 16, 2020 2:15 pm
Hmm, on more careful reading, it seems it might be the other way around: we are feeding in a lower Vreg. I'm feeling confused now!
The Spectrum ULA description is quoted thus: "CML arrays permitted the use of two separate supply voltages for Vcc and Vreg, producing a lower power dissipation without compromising speed" so it's entirely likely that the reduced Vreg is simply to reduce the dissipation on a chip which already runs too hot for comfort.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sun Aug 16, 2020 2:33 pm

Ah, good point, that works for me - if there's no effect on speed, and we're running too hot, it's a good plan.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Coeus » Sun Aug 16, 2020 2:49 pm

Richard Russell wrote:
Sun Aug 16, 2020 2:22 pm
If it is a termination, I doubt that the impedance will have been determined 'scientifically'; it's more likely that Acorn will have tried a few resistor values to see which had the desired effect...
Which are the resistors that were put in to a substitute for Steve Furber's finger? I refer to the story that things started working when he put his finger on the board somewhere. If it is these then that lends weight to the idea of trial and error rather than rigorous design.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by BigEd » Sun Aug 16, 2020 2:53 pm

I believe that's RP1, the 6k8 resistor pack which pulls the databus towards ground.

But I agree with the idea that there was some trial and error going on.

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Re: VIDPROC V2 (pin 15) - please explain!

Post by Coeus » Sun Aug 16, 2020 3:28 pm

Richard Russell wrote:
Sun Aug 16, 2020 10:21 am
...So maybe I'm wide of the mark, but the resistors aren't likely to be having any significant effect on DC logic levels (the output of the S00 is too low impedance, even in the logic 1 state, for that to be the case) so a high-frequency function seems more plausible.
Do we know what the output impedance is? Can this be approximated to the 50Ω between the collector of the upper output transistor and VCC? If so, 500Ω being 10x 50Ω has someone applied the old 10X rule?

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