I wonder if the poor little chip might achieve the AI singularity if we.... wrote 6 to the register

I wonder if the poor little chip might achieve the AI singularity if we.... wrote 6 to the register
It's possible that I had different electrical properties because at the time of my tests, I had a Chinon F-051MD drive attached.Diminished wrote: ↑Fri Sep 04, 2020 12:27 amYeah, I can't trivially reproduce what you did, Chris. I can find values which put a 25 KHz square wave on LOAD HEAD and a 400 KHz square wave on INT, and I can find values which pull either or both of those pins high, but I'm not seeing the crazy superposition that you reported.
I think the problem I’m having cleaning this die is because it’s glued to the bottom of the ceramic package, so I have to put the whole thing into acid, not just the die. With a plastic package, I could get to just the die (maybe still attached to the metal paddle, but that’s something I’m used to).
I hate to destroy another chip unless someone thinks it would help. Cole seems to think there’s enough detail in my pics to vectorize it, so maybe we wait and see if there’s an issue.
I also uploaded a top metal die shot of the 8273: www.seanriddle.com/8271/8273metal.jpg
I see it says (c) 1979... maybe there were some fixes in later chips.Diminished wrote: ↑Sat Sep 05, 2020 11:45 pmThe chip isn't quite the same as the 8271 though! There are differences here and there.
It's great to hear that people are still working on this. I'm also still regularly looking at the opcodes to try and make something fit, but it is a royal PITA.
Eventually! I keep picking away at it like a scab, but there's a whole lot of logic to dig into between the bus and the PLAsscarybeasts wrote: ↑Sun Sep 06, 2020 12:06 amIs there any hope of tracing the opcode bits through the PLA so see which opcode bit combinations activate what? Even identifying just a few critical opcodes could be enough to cause a cascade of successful opcode inference.
Are you happy with how that works? It's not too hard to decode.
What I'm seeing is a load and a recirculate control: the two inverters which capture the input value are in a broken loop. This is a commonly seen 'register' circuit.
Aha! So what we probably have is a clock, which precharges the rows, and then they are conditionally discharged. An actively switched pullup is not so common, but they are seen. Because pullups are a bit rubbish compared to pulldowns, sometimes it makes sense to pull up unconditionally and then pull down conditionally.The lower input apparently pulling down both column lines at the same time as turning on the pull up for all the rows puzzles me too.
Great job!
Code: Select all
111x xxxx E0-FF
0001 xxxx 10-1F
1111 1100 FC
1111 1101 FD
01xx xxxx 40-7F
1111 1110 FE
1000 1xxx 88-8F
1110 11xx EC-EF
1111 1111 FF
0001 xxxx 10-1F
1111 1000 F8
1010 1xxx A8-AF
1001 1011 9B
1001 01xx 94-97
1001 1100 9C
1100 xxxx C0-CF
0111 xxxx 70-7F
111? 10xx E8-EB, F8-FB ??
1001 1101 9D
1101 xxxx D0-DF
1110 1001 E9
1111 1001 F9
1001 1011 9B
100x 01xx 84-87, 94-97
10xx 0xxx 80-87, 90-97, A0-A7, B0-B7
0010 xxxx 20-2F
1010 1xxx A8-AF
1111 1000 F8
1001 1000 98
11xx 0xxx C0-C7, D0-D7, E0-E7, F0-F7
1111 0xxx F0-F7
1001 110x 9C-9D
101x 0xxx A0-A7, B0-B7
1111 1001 F9
1110 1100 EC
0011 xxxx 30-3F
1110 1000 E8
110x 1xxx C8-CF, D8-DF
01xx xxxx 40-7F
10xx 0xxx 80-87, 90-97, A0-A7, B0-B7
001x xxxx 20-3F
Here's one interesting thing, Rich -- there are fourteen columns in the left table which don't have any don't care-looking thingies in them.Rich Talbot-Watkins wrote: ↑Sun Sep 06, 2020 6:10 pmIncidentally, one mystery I'd like to solve is how 2 byte opcodes are described. There doesn't seem to be much of a pattern in that, and I imagine that, of all those signals, some of them will be OR'd together to specify 2 byte opcodes. (I guess the signal is then latched, and causes the subsequent instruction to be fetched to a temporary register instead of the instruction register, given the apparent absence of any timing signal to the PLA).
They're not quite the same opcodes (although there is overlap) but I don't think they need be.Diminished wrote: ↑Sun Sep 06, 2020 6:29 pmHere's one interesting thing, Rich -- there are fourteen columns in the left table which don't have any don't care-looking thingies in them.
And the number of columns in the right table which don't have any don't care-looking thingies in them is ... also fourteen.
Money's on them being the same opcodes.
I'm concerned a bit about those three columns in the right table which don't appear to be connected to anything whatsoever. I might trace those lines later and see if they actually go anywhere.
Code: Select all
1001 1010 9A
1110 1101 ED
1011 1xxx B8-BF
1010 1xxx A8-AF
1111 1111 FF
1110 1001 E9
1000 10x1 89, 8B
01x1 xxxx 50-5F, 70-7F
1000 1100 8C
01xx xxxx 40-7F
1000 100x 88, 89
xxxx xxxx 00-FF
xxxx xxxx 00-FF
xxxx xxxx 00-FF
1000 101x 8A, 8B
110x 1xxx C8-CF, D8-DF
100x 110x 8C, 8D, 9C, 9D
100x 1011 8B, 9B
1110 1011 EB
1001 01xx 94-97
101x 0xxx A0-A7, B0-B7
100x 01xx 84-87, 94-97
1011 0xxx B0-B7
1001 00xx 90-93
1110 1010 EA
1111 1001 F9
10xx 0xxx 80-87, 90-97, A0-A7, B0-B7
1110 0xxx E0-E7
110x 0xxx C0-C7, D0-D7
1011 1xxx B8-BF
0001 xxxx 10-1F
1111 1111 FF
xxxx xxxx 00-FF
0xxx xxxx 00-7F
011x xxxx 60-7F
1001 1100 9C
1000 00xx 80-83
1100 xxxx C0-CF
1001 110x 9C, 9D
1001 1000 98
1111 0xxx F0-F7
1000 1xxx 88-8F
1111 11xx FC-FF
10xx 0xxx 80-87, 90-97, A0-A7, B0-B7
0011 xxxx 30-3F
11xx 0xxx C0-C7, D0-D7, E0-E7, F0-F7
0000 xxxx 00-0F
1110 11xx EC-EF
1010 1xxx A8-AF
0001 xxxx 10-1F
1110 1000 E8
1111 1000 F8
1001 1011 9B
100x 01xx 84-87, 94-97
1111 0xxx F0-F7
110x xxxx C0-DF
0010 xxxx 20-2F
01xx xxxx 40-7F
Checked them, and indeed, they don't seem to be!Diminished wrote: ↑Sun Sep 06, 2020 6:29 pmI'm concerned a bit about those three columns in the right table which don't appear to be connected to anything whatsoever. I might trace those lines later and see if they actually go anywhere.
Thanks, yes, it seems likely, but I have zero IC design experience!