CRTC timing with 2MHz clock

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Rich Talbot-Watkins
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CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 2:07 pm

Throwing a question out there to anyone who understands this hardwarey stuff more than I do.

The 6845 CRTC can operate on the Beeb at two clock speeds - 1MHz and 2MHz - according to bit 4 of the Video ULA. I assume this controls not just its character clock rate, but also the rate at which its registers are accessed (I don't see two separate clock inputs).

We also know that writes to &FE00/&FE01 are cycle-stretched to 1MHz, even when the CRTC is running at 2MHz.

My question here is: given this mismatch of clocks in high-clock modes, is there any possibility that CRTC register writes could happen before the 6502 write cycle has finished? During the stretched 6502 write cycle, the CRTC will see either 2 or 3 cycles - is it feasible that these could manifest themselves as double or even treble accesses to the CRTC?

I'm trying to find an explanation for something observed on real hardware, whereby a register write appeared to be taking place earlier than expected.

I guess this is probably something that only a scope can really 'prove', but it'd be interesting if anyone could confirm the possibility at least!

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Re: CRTC timing with 2MHz clock

Post by cmorley » Sun Sep 15, 2019 2:15 pm

Cycle stretching is a poor term. The machine does clock domain crossing. The processor is forced onto the 1MHz clock which remains constant and synchronous. So it is always deterministic - a feature I used for cycle counting on the mode 0 Bad Apple demo. I inserted (reordered) 2 or 3 cycle instructions into the instruction stream ahead of writes to the sound chip (via the 6522) so I wasted as few cycles as possible - force the CPU synchronous to the 1MHz clock with my code so no wait cycle.
Last edited by cmorley on Sun Sep 15, 2019 2:16 pm, edited 2 times in total.

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 2:27 pm

That's not exactly my understanding of it.

This diagram from the AUG
Image
shows that it's not switching in the 1MHz clock so much as actually stretching one cycle over three.

It is certainly deterministic; if you have just synchronised to a 1MHz device by accessing one, then you can always know the timing of a subsequent 1MHz access. For example:

Code: Select all

STA &FE00   ; sync to 1Mhz
LDX #32     ; 2 cycles
STX &FE01   ; instruction takes 6 2MHz ticks

Code: Select all

STA &FE00   ; sync to 1MHz
LDX &70     ; 3 cycles
STX &FE01   ; instruction takes 5 2MHz ticks
But anyway, my question is still open. Depending upon at which point the 6502 pulls R /W low, puts FE01 on the address bus and the register on the data bus, is it possible that the CRTC (running at 2MHz) could get this write at an earlier point than normal, given that it will see 2 or 3 whole cycles during this time?

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 2:45 pm

Even better, if anyone can see with a scope what's going on with the 6502 A15, phi1, phi2 and R/W pins, and with the 6845 CLK, R/W, E and /CS pins while this program runs, that'd be amazing information!

Code: Select all

10 MODE 0:REM high clock mode
20 P%=&900:[OPT2:SEI:.loop LDA #0:STA &FE00:LDA #80:STA &FE01:JMP loop:]
30 CALL &900
(Aside: why does the CRTC need both Chip Select and Enable pins?)

This is all in the name of trying to improve jsbeeb and other emulators to run some very fragile CRTC effects which need perfect timing. I mean, really perfect!
Last edited by Rich Talbot-Watkins on Sun Sep 15, 2019 2:51 pm, edited 1 time in total.

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Re: CRTC timing with 2MHz clock

Post by tom_seddon » Sun Sep 15, 2019 3:11 pm

I'd always thought it was just the high clock period (T...U here) that got stretched, as per Matt's jsbeeb article: https://xania.org/201405/jsbeeb-getting ... -right-cpu - but this diagram appears to show the low clock period stretched too!

Unfortunately I don't have the skills to figure out what's really happening from the circuit diagram...

--Tom

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 3:14 pm

tom_seddon wrote:
Sun Sep 15, 2019 3:11 pm
I'd always thought it was just the high clock period (T...U here) that got stretched, as per Matt's jsbeeb article: https://xania.org/201405/jsbeeb-getting ... -right-cpu - but this diagram appears to show the low clock period stretched too!

Unfortunately I don't have the skills to figure out what's really happening from the circuit diagram...

--Tom
Yeah that's actually why I'd quite like to see what happens via a logic analyser. That diagram in Matt's blog came from me (I think!) but I don't remember where I previously saw this.

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Re: CRTC timing with 2MHz clock

Post by cmorley » Sun Sep 15, 2019 3:16 pm

There are two cases for the clock crossing. Only one is shown in the NAUG (and App note 3). The other one is the low phase of the 2MHzE is 250ns and high phase is 750ns (75% duty cycle).

The falling edge of 1MHzE and 2MHzE always coincide.

Writes from CPU -> device latch at this falling edge.

The CPU 2MHzE is always 250:750 for all 1MHz accesses - there is just a variable low phase to get syncronous with the 1MHzE.

So there will always be 1.5 cycles of the 2MHz clock when the 2MHzE is high (h-l-h).

edit: The 6845 enable comes from the 1MHzE anyway so a write will only ever overlap one 2MHz cycle.
Last edited by cmorley on Sun Sep 15, 2019 3:39 pm, edited 1 time in total.

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Re: CRTC timing with 2MHz clock

Post by cmorley » Sun Sep 15, 2019 3:23 pm

Yellow = 2MHzE
Blue = 1MHzE

even case:
NewFile1.png
odd case:
NewFile2.png
Both cases the clock is 75% duty synchronous to the 1MHzE.

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 3:56 pm

cmorley wrote:
Sun Sep 15, 2019 3:16 pm
There are two cases for the clock crossing. Only one is shown in the NAUG (and App note 3). The other one is the low phase of the 2MHzE is 250ns and high phase is 750ns (75% duty cycle).

The falling edge of 1MHzE and 2MHzE always coincide.

Writes from CPU -> device latch at this falling edge.

The CPU 2MHzE is always 250:750 for all 1MHz accesses - there is just a variable low phase to get syncronous with the 1MHzE.

So there will always be 1.5 cycles of the 2MHz clock when the 2MHzE is high (h-l-h).
Ah, that's great information, much appreciated (and thanks for the scope traces)!

So, the next part of the question is: with the CRTC running on a 2MHz clock while accesses to it from the CPU are cycle stretched in this way, could the CRTC get a write before the end of the 'stretched' cycle?

For example
20190915_174629.jpg
Normally writes to 1MHz devices will happen at point Q, when the 1MHzE edge falls.

But the CRTC is getting a 2MHz clock at this point. So, by point P, has the 6502 set up all the relevant signals (R/W low, address bus, data bus) such that the 6845 could get a write 1 cycle early in this case (on its falling 2MHz edge)? This would also depend on the 6845 chip select etc having been set up correctly. This is what I'm interested in, as I'm trying to explain observed effects on real hardware that suggest that 6845 register writes are happening earlier than expected.
Last edited by Rich Talbot-Watkins on Sun Sep 15, 2019 4:03 pm, edited 1 time in total.

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Re: CRTC timing with 2MHz clock

Post by cmorley » Sun Sep 15, 2019 4:02 pm

No because the bus is controlled by E (enable) which is 1MhzE. The character generation is done from CLK (clock).
6845 bus.png

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 4:11 pm

Ah, yeah. And I see it in the circuit diagram now as well.

Do you think there's any possibility it might be happening on the 1MHz cycle before Q, or is that too premature for the CPU to have set things up?

Thanks for your expertise!

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Re: CRTC timing with 2MHz clock

Post by cmorley » Sun Sep 15, 2019 5:05 pm

Do you mean could E act as enable for a latch rather than a clock for a flip flip (register)?

I doubt it or the internals of the 6845 would be subjected to all the spurious data bus values while the data is being set up. Note the datasheet requires the data to be setup before the end of E high not at the start before E goes high. I expect the writes to be registered on the falling edge of E. So the register will retain the previous value right up to the falling edge of E.

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Re: CRTC timing with 2MHz clock

Post by BigEd » Sun Sep 15, 2019 5:30 pm

In the case of a '2MHzE even' clock shape, it does look like there's a falling edge on 1MHzE a full cycle before time Q, and yes, I would expect the 6502 and glue logic to have done all the necessary things by this time. (I say that without having studied the schematic.)

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Sun Sep 15, 2019 7:22 pm

BigEd wrote:
Sun Sep 15, 2019 5:30 pm
In the case of a '2MHzE even' clock shape, it does look like there's a falling edge on 1MHzE a full cycle before time Q, and yes, I would expect the 6502 and glue logic to have done all the necessary things by this time. (I say that without having studied the schematic.)
Is this what's being alluded to in the AUG 28.5.2 perhaps (with reference to the diagram I attached earlier)?
AUG wrote: 28.5.2 Double accessing of 1MHz bus devices - PROBLEM 2

If a 1MHz bus device is accessed during a period when the 1MHzE clock is high (point ‘R’ in figure 28.2), that device will be accessed immediately. The device will then be accessed again when 1MHzE is next high (point ‘V’ in figure 28.2). This is because the CPU clock is held high until the next coincident falling edge of the 2MHz and 1MHz clocks (point ‘U’). Double accessing a peripheral does not normally present a problem. However, if reading from or writing to a device has some other function, such as clearing an interrupt flag, a problem may occur.

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Re: CRTC timing with 2MHz clock

Post by cmorley » Sun Sep 15, 2019 7:54 pm

The NAUG/AUG is talking about the 1MHz bus.

The 6845 chip select signal ~CRTC comes from IC26. The gate (output enable) for IC26 comes from IC29 an or gate where high bits address match is ORed with phi1.

So single access only for the CRTC.
crtc decode.png

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Re: CRTC timing with 2MHz clock

Post by Rich Talbot-Watkins » Fri Oct 04, 2019 4:09 pm

Conclusion to this curious bit of archaeology here.

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