Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

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bprosman
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Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Thu Aug 08, 2019 11:30 am

Currently I am experimenting (again) with Xilinx CPLD's. In the past using Altera there was a library to build a schematic using TTL replacements from a library. That was easily translated into an EPM3064.
In Xilinx I actually dont find this functionality, I am looking into "translating" a schematic with 74LS138/74LS139 and a 74LS670 into a XC9536 or XC9572.

Anyone having handy tips ? Schould I go the VHDL way ? or "rebuild" the chips from the datasheet using the basic ports ?

Thanks in advance for the answers.

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hoglet
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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by hoglet » Fri Aug 09, 2019 6:12 am

bprosman wrote:
Thu Aug 08, 2019 11:30 am
Anyone having handy tips ? Schould I go the VHDL way ? or "rebuild" the chips from the datasheet using the basic ports ?
As far as I know, Xilinx never released a TTL Library for the XC9500XL series CPLDs. One reason is that accurately modelling certain parts is difficult, as I don't think the XC9500XL series can mimic a transparent latch (like a 74LS373/573).

I would suggest going the Verilog or VHDL way.

Dave

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Fri Aug 09, 2019 6:14 am

Hi Dave,

First of all thanks for the swift reply.
I did found some VDL sources :
https://github.com/Idorobots/upnod-card ... r/vhdl/src

For me this looks understandable. Next thing (to learn) is to how to connect "Real signals" (eg an address line) to a VHDL "74ls139" for example.

Thanks a lot.
Bram

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by hoglet » Fri Aug 09, 2019 6:38 am

bprosman wrote:
Fri Aug 09, 2019 6:14 am
For me this looks understandable. Next thing (to learn) is to how to connect "Real signals" (eg an address line) to a VHDL "74ls139" for example.
For a small design, I would recommend flattening everything so that you are just dealing with a single module.

The reason I say this is that I've been helping Roland add interrupt capability to the UART in the AtomGodilVideo module that Atom FPGA uses. Almost all of the issues he encountered were errors trying to wire the modules together. This is one of the worst aspects I think of VHDL, because it's verbose and over complicated.

If you can keep everything in one module, it's much easier to undertand what's going on, and to spot logic errors (as opposed to wiring errors). It also means you focus on the "business logic" of the design right from the start.

Can you post the complete schematic you are trying to re-engineer?

Dave
Last edited by hoglet on Fri Aug 09, 2019 6:41 am, edited 2 times in total.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Fri Aug 09, 2019 7:27 am

Can you post the complete schematic you are trying to re-engineer?
Sure , here it is, a memory mapper "stolen" from a few other designs :
I hoped to fit it in an XC9536 or XC9572 (44 pin).

As mentioned, I found some VHDL definitions of the chip here :
https://github.com/Idorobots/upnod-card ... r/vhdl/src
Memory Paging.JPG
D0-D7 are inputs from the CPU'
A0-A1, A2, A14-A15 are inputs from the CPU
RESET is an input from the CPU
/MREQ is an input from the CPU
/CFG_CS is an external CS signal

MA14-MA21 are outputs to the memory chip
ROM_CS, RAM_CS are outputs to the memory chips

/PAGE_EN, /PAGE_WR, /PGEN_WR are "Internals"
Last edited by bprosman on Fri Aug 09, 2019 7:35 am, edited 1 time in total.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by cmorley » Fri Aug 09, 2019 7:43 am

Atmel still make and sell 5V CPLDs which are equivalent to the EPM30xx. So much so they provide a POF2JED so you can use the Altera tools and just convert the POF file to a JED file.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by Prime » Fri Aug 09, 2019 11:09 am

Taking a quick look at your schematic.....

You have two latches that are 4x4, one of which latches d0..d3, the other d4..d7, so these can be treated as a 4x8. This means you are going to need 32 bits of latches so, at a guess I'd say you'd be pushed to fit this into a 9536, as there's only one flipflop/latch per macrocell. But should fit into a 9572 without problems. The rest of the logic on there is combinational so should pack in vairly well.

Cheers.

Phill.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by Prime » Fri Aug 09, 2019 11:52 am

Ok, having tried things out in Webpack, something like the following......

Code: Select all

module decoder(
    input 	[7:0] D,		// Data bus from CPU (Z80???)
    input 	[2:0] AL,		// Address bus low bits
    input 	[15:14] AH,		// Address bus high bits
    input 	nRESET,			// System reset
    input 	nMREQ,			// Memory request
    input 	nCFGCS,			// Config chip select
    input 	nWR,			// Write strobe
    
	output 	[21:14] MA,		// Mapped address lines
    output	nROMCS,			// ROM chip select
    output 	nRAMCS,			// RAM0 chip select
    output 	nRAMCS1,		// RAM1 chip select
    output 	nRAMCS2			// RAM2 chip select

    );


reg [7:0] MALat [3:0];		// array of latches 8 bits wide x 2 bits deep.
reg nPAGEEN;				// Single bit page enable latch.

// First decodeer to generate nPAGEWR and nPAGEENWR
assign	nPAGEWR 	= !(!nWR & !nCFGCS & !AL[2]);
assign	nPAGEENWR 	= !(!nWR & !nCFGCS & AL[2]);

// Now decode nROMCS and nRAMCSx
assign 	nROMCS		= !(!nMREQ & !MA[20] & !MA[19]);
assign 	nRAMCS		= !(!nMREQ & !MA[20] &  MA[19]);
assign 	nRAMCS1		= !(!nMREQ &  MA[20] & !MA[19]);
assign 	nRAMCS2		= !(!nMREQ &  MA[20] &  MA[19]);

// Setup to address the array
wire [1:0] LatA;			
assign LatA[1:0] = AL[1:0];

// Latch MA lines when nPAGEWR is asserted low.
always @(negedge nPAGEWR)
begin
  MALat[LatA[1:0]] <= D[7:0];
end

// PageEn write logic, if Reset is asserted then reset PAGEEN
// else if nPAGEENWR is asserted, then PAGEEN is latched from D0.
always @(negedge nPAGEENWR or negedge nRESET)
begin
  if (!nRESET)
    nPAGEEN <= 1'b1;
  else
    nPAGEEN <= !D[0];
end

// MA outputs
wire [1:0] LatO;
assign LatO[1:0] = AH[15:14];

// If nPAGEEN is low then assign the appropreate latch to the MA outputs
// else tristate if nPAGEEN is high
assign MA[21:14] = nPAGEEN ? 8'bz : MALat[LatO[1:0]];

endmodule
Can confirm that the above won't fit in a 9536 but will in a 9572.

Cheers.

Phill.
Last edited by Prime on Fri Aug 09, 2019 11:54 am, edited 1 time in total.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Fri Aug 09, 2019 12:01 pm

@Phill,

Many thanks !!
This will give me a nice headstart.
XC9572 is not an issue as it is there in a 44pin (SMD) version so not too much of a footprint.

Kind regards, Bram

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by Prime » Fri Aug 09, 2019 12:05 pm

bprosman wrote:
Fri Aug 09, 2019 12:01 pm
@Phill,

Many thanks !!
This will give me a nice headstart.
XC9572 is not an issue as it is there in a 44pin (SMD) version so not too much of a footprint.
Indeed and the nice thing is where the different members of the family are in the same packages they are generally pinout compatible, meaning if you find that you run out of space in say a 9536-vq44, you can swap to a 9572-vq44, just by re-compiling.

One point of caution, though the code above compiles OK I don't have the hardware so it's untested :)

Cheers.

Phill.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Fri Aug 09, 2019 12:23 pm

One point of caution, though the code above compiles OK I don't have the hardware so it's untested :)
No problem :-) I take that part.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by roland » Fri Aug 09, 2019 2:13 pm

hoglet wrote:
Fri Aug 09, 2019 6:38 am
The reason I say this is that I've been helping Roland add interrupt capability to the UART in the AtomGodilVideo module that Atom FPGA uses. Almost all of the issues he encountered were errors trying to wire the modules together. This is one of the worst aspects I think of VHDL, because it's verbose and over complicated.
And I still don't really know whether I understand this technique or not :-k Adding the real time clock in an existing module was so much easier 8)
256K + 6502 Inside
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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Sat Aug 10, 2019 9:56 am

@Roland,

Reading the example (headstart) that was given me I do sort of understand what is going on.

Got it compiled in my own ISE (14.7) version here. Created a UCF file to have the signals a little more arranged.

Creating the PCB now (in Kicad) , I’m here in Italy for another week, Tuesday I will send off the PCB’s to JCLPCB so that they will arrive home when I do.

One more question , just curiousity : Unassigned pins are mapped and marked as KPR. Where does KPR stand for ?

Kind regards, Bram

P.S. Agreed with my son that the next curious one asking what we are doing on a laptop on a camping site ( playing with Kicad) we will tell we’re actually from Russia hacking the Italian government network 😉 ( We had at least a dozen asking 😉)
Last edited by bprosman on Sat Aug 10, 2019 9:59 am, edited 1 time in total.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by Elminster » Sat Aug 10, 2019 10:09 am

bprosman wrote:
Sat Aug 10, 2019 9:56 am

P.S. Agreed with my son that the next curious one asking what we are doing on a laptop on a camping site ( playing with Kicad) we will tell we’re actually from Russia hacking the Italian government network 😉 ( We had at least a dozen asking 😉)
Seems to be a running theme. ‘What odd things did you take on holiday this year’. I was think about taking a few FPGAs to carry on playing with them in the evenings on my next holiday’

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by bprosman » Sat Aug 10, 2019 10:12 am

Nothing really odd. A little case with some Arduino stuff but my son (22) took his laptop for the first time so we’re with 2 now. Mainly playing with Kicad.
Last edited by bprosman on Sat Aug 10, 2019 10:13 am, edited 1 time in total.

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by Elminster » Sat Aug 10, 2019 10:14 am

I think that is subjective. If it wasn’t odd you wouldn’t be having lots of people asking you what you were doing :)

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Re: Discrete logic (TTL) into a CPLD (XC9536 or XC9572).

Post by roland » Sat Aug 10, 2019 11:07 am

AFAIK are KPR (stands for keeper) pins unconnected inputs that are tied through a high resistor to a high or low level. Some designers prefer to make unused pins an output with a fixed output (high or low).
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