Master IO Controller IC15 - Databus pins?

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simoni
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Master IO Controller IC15 - Databus pins?

Post by simoni » Sat Apr 13, 2019 10:41 am

The IO Controller IC15 in the Master (CF30050) has two data pins D4 and D5 connected to the CPU databus CD4 and CD5.

Does anyone know why? :)

(Even better if someone can point me in the direction of some reverse engineering for this chip)

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MartinB
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Re: Master IO Controller IC15 - Databus pins?

Post by MartinB » Sat Apr 13, 2019 11:24 am

This doesn't really answer your question but perhaps offers a clue in that checking the integrity of those two pin connections is called up in the Master Service Manual in the context of fault-finding both the 1MHz Bus and the Tube.... :-k

IC15.JPG

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Re: Master IO Controller IC15 - Databus pins?

Post by dp11 » Sat Apr 13, 2019 11:28 am

There are used to select between internal and external tube and 1MHz bus. ( fe34)
Last edited by dp11 on Sat Apr 13, 2019 11:29 am, edited 1 time in total.

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Re: Master IO Controller IC15 - Databus pins?

Post by dp11 » Sat Apr 13, 2019 11:39 am

If you haven't see this thread , it might be worth a read . viewtopic.php?f=3&t=13964&p=184473&hilit=IC15#p184473

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Re: Master IO Controller IC15 - Databus pins?

Post by simoni » Sat Apr 13, 2019 11:46 am

There are used to select between internal and external tube and 1MHz bus. ( fe34)
Thanks! Makes a lot of sense :) &FE34 is the ACCCON register though... the documentation (Acorn engineering news 1) says that ACCCON is contained in the Memory Controller though (IC20):

https://github.com/simoninns/Acorn-Mast ... gNews1.pdf

Which is why I was a bit confused... I guess the Acorn engineering note is wrong then?

Ah, just seen your link (popped up as I was typing this); I will have a read through.

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