Logic Levels for 5V TTL Systems

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1024MAK
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Logic Levels for 5V TTL Systems

Post by 1024MAK » Thu Nov 08, 2018 11:23 am

The voltages of the signals in most 5V logic systems is based on the TTL logic levels. As most microprocessor systems used 74xxx or 74LSxxx or related series chips for at least some functions.

Hence when NMOS chips replaced the bipolar transistor logic chips, the NMOS chips were designed to be compatible with TTL logic levels. Later on, as CMOS memory chips were designed, again a lot of these were designed to interface to microprocessors. So it was logical for CMOS microprocessors and other support chips to again be designed to be compatible with TTL logic levels when operated on a 5V supply. Note however that the CMOS chips output drivers (output pins) can drive the output much closer to the +5V supply compared to the figure shown in the diagram below. Also the input switching levels may not be exactly the same as in the diagram below. Always refer to the relevant datasheet for the chips you are using.

This diagram shows the TTL logic levels:-
DC9C1FC6-468F-46ED-839A-BC497CD7F547.png
TTL Logic Levels
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Richard Russell
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Re: Logic Levels for 5V TTL Systems

Post by Richard Russell » Thu Nov 08, 2018 1:01 pm

1024MAK wrote:
Thu Nov 08, 2018 11:23 am
So it was logical for CMOS microprocessors and other support chips to again be designed to be compatible with TTL logic levels when operated on a 5V supply.
It might be helpful to make a distinction between the 74HC and 74HCT ranges of CMOS logic chips; the former do not have TTL-compatible input thresholds whereas the latter do. The 4000-series CMOS logic devices don't have TTL-compatible inputs either.

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Re: Logic Levels for 5V TTL Systems

Post by BigEd » Thu Nov 08, 2018 1:12 pm

I often end up finding this diagram:

Image

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Re: Logic Levels for 5V TTL Systems

Post by flynnjs » Wed Nov 14, 2018 7:56 am

Yes, I often find that useful, although it misses the fact the SOME low voltage systems are 5v tolerant on input.

For example, I'm curently using some 3v LVC buffers and sticking 5v into them which is OK according to the device's datasheet.

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Re: Logic Levels for 5V TTL Systems

Post by dominicbeesley » Wed Nov 14, 2018 10:04 am

And there's LVTTL levels which will drive 5v TTL parts but not CMOS... that's got me a few times. The 65816 and 65c02 chips need strong CMOS levels on their clock pins or they misbehave. I spent months debugging a problem on my first 65816 project that appeared to be a timing problem but was cured by strengthening the clock signals

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Re: Logic Levels for 5V TTL Systems

Post by 1024MAK » Wed Nov 14, 2018 10:17 am

dominicbeesley wrote:
Wed Nov 14, 2018 10:04 am
And there's LVTTL levels which will drive 5v TTL parts but not CMOS... that's got me a few times. The 65816 and 65c02 chips need strong CMOS levels on their clock pins or they misbehave. I spent months debugging a problem on my first 65816 project that appeared to be a timing problem but was cured by strengthening the clock signals
Yeah, but CPU clock signals rarely are to TTL levels. For example, apart from 65C02 and 65816 CPUs, the original NMOS Z80 CPUs need a logic high on their clock input pins that is higher than the typical TTL gate (74xxx or 74LSxxx) can manage. And all clock signals normally have to have relatively fast rise and fall times.

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Re: Logic Levels for 5V TTL Systems

Post by dominicbeesley » Wed Nov 14, 2018 11:40 am

I know, its just another thing that needs to go on the list of gotchas with logic levels, along with the "compatible" LVCMOS and LVTTL levels popular on some FPGAs. On the 65* NMOS processors it is fall time rather than rise time that's the killer, the original 6502 could tolerate (and generated) slow to rise clocks. The 65816 and 65c02 are very picky though and seem to (un)happily clock away on noise on a rising edge whilst ignoring any signals that don't go reliably and quickly to over 3.5V then seemingly work fine on out of spec signals for days. I have to admit having originally mis-read the spec for the w65c02 which has two sets of figures in the same row for two different sets of signals.

[on the 65c02 chips it's not just the clocks but also RES, IRQ, NMI, SO on the 65816 its everything though it seems to accept lower than spec levels for the D lines...for quick and dirty work I've found that the z80 will work ok with a lowish (1k) pull up resistor on its clock inputs when I've wanted a lash-up and only had a TTL buffer for the clock]

Here's a diagram that I have on call from EEtimes (https://www.eetimes.com/document.asp?doc_id=1231111) it shows the LV levels too which can be handy when working with new fangled stuff
Attachments
Fig1.gif

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Re: Logic Levels for 5V TTL Systems

Post by bprosman » Wed Nov 14, 2018 3:55 pm

Always found this a quick and easy design for a level shifter :
https://learn.sparkfun.com/tutorials/bi ... -guide/all

Based on NXP's appnote :
https://www.nxp.com/docs/en/application ... N10441.pdf

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Re: Logic Levels for 5V TTL Systems

Post by flynnjs » Wed Nov 14, 2018 5:36 pm

The topic has drifted quite a lot to clocks so I'll mention that I've been
checking out the clock into a XC9500XL which is 5v tolerant.
Last night I used the Arb to generate clock pulses with various
rise/fall times but all supposedly monotonic (and so that seemed
on the high BW 'scope).
With a rising edge flip-flop it needs faster than 200ns rise and 500ns
fall. Any longer than that and the system starts glitching quite badly.
I suspect the slow clock causes high current draw which then makes
the supply droop and changes the threshold causing multiple triggers.

The system I'm interfacing has a horrible RC circuit on the line
driving the clock as a filter as it's in a harsh RF environment. I'm
going to have to put it through a Schmitt buffer to clean it up.

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Re: Logic Levels for 5V TTL Systems

Post by bprosman » Wed Nov 14, 2018 8:29 pm

Any longer than that and the system starts glitching quite badly.
Maybe a little off topic but i'm struggling with a XC9572XL driven by a DIL oscillator but after some time the CPLD freezes.
The oscillator is powered with 5V, the CPLD with 3V3.
Last edited by bprosman on Wed Nov 14, 2018 8:30 pm, edited 1 time in total.

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Re: Logic Levels for 5V TTL Systems

Post by flynnjs » Thu Nov 15, 2018 7:46 am

bprosman wrote:
Wed Nov 14, 2018 8:29 pm
Maybe a little off topic but i'm struggling with a XC9572XL driven by a DIL oscillator but after some time the CPLD freezes.
The oscillator is powered with 5V, the CPLD with 3V3.
If the oscillator block is high drive and only driving a light load then
you might find it's ringing and overshooting 5v considerably which
could cause a problem like that. You also need to be very careful
with power sequencing, the XC9500XL MUST be powered before
applying any 5v IO signals or it will nuke itself.

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Re: Logic Levels for 5V TTL Systems

Post by bprosman » Tue Dec 18, 2018 11:38 am

@Flynnjs,

Think I nailed it, put an extra (10uF Tantalium) capacitor on the power line and a 1K resistor in series with the clock signal. Its running now already for more than 15 hours without freezing.

Kind regards, Bram

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