Converting ABR to EEPROM (28C256) for the Master

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daveejhitchins
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Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Sat Aug 11, 2018 1:48 pm

This thread was for the Electron - which turned out to be easy e.g. just removing the battery and replacing the SRAM with the 28C256 Flash/EEPROM worked. The ABR for the Master seems to be causing me problems :?

First I tried exactly what I did for the Electron - Master wouldn't even start-up. Hmmmm! Time to look closly at what I was doing inside the PLD (GAL16V8 25ns/15ns < tried both). I couldn't see anything obvious - so:

Just picked up this issue again, as it was starting to bug me. I'd had some suggestions form Steve Picton (thanks Steve) - I'll list what I've done since restarting the investigation.

I'd been reading MartinB's thread EEPROM - the Holy Grail of Sideways Rom? - although I haven't one of Spro's boards I have my ARA II board. They're a little tricker to modify as pin one is connected to +5V - However, I modified a bare PCB so it was easy. The result was I have a working ARA II board with a 28C256 plugged into it.

Next . . . To take some reference 'scope shots, ARA II, of the three control signals: nCS, nOE and R/nW
Top trace down = T2, nCS, Noe and R/nW (for all 'scope traces)
ref1.jpg
Showing a write followed by a read to the EEPROM
ref2.jpg
Showing the write in more detail
ref3.jpg
Showing the read in more detail
All Martin's EEPROM utilities work just fine.

Next . . . Change the ABR PLD code to match Martin's changes here. Code now looks like this:

Code: Select all

Name     ABRMasterTest ;
PartNo   16L8 ;
Date     10/08/2018 ;
Revision 01 ;
Designer DaveH ;
Company  StarDot ;
Assembly ABR ;
Location  ;
Device  g16v8a ;

/***************** INPUT PINS ******************************************/
PIN 1   =  NOE                    ; /* Not-Output Enable               */ 
PIN 2   =  ERNW                   ; /* Electron Write & Master Select  */ 
PIN 3   =  QA                     ; /* Page latch LSB - 16A EC         */ 
PIN 4   =  A1                     ; /* Address line 1 - 17B EC         */ 
PIN 5   =  A0                     ; /* Address line 0 - 18B EC         */ 
PIN 6   =  T2                     ; /* CPU clock phase 2               */ 
PIN 7   =  A5                     ; /* Address line 5 - 13B EC         */ 
PIN 8   =  MADET                  ; /* Master detect - Low if Master   */ 
PIN 9   =  MRNW                   ; /* Master Write                    */ 
PIN 11  =  NA23467                ; /* N&'ed add. lines 2,3,4,6 & 7    */ 
PIN 15  =  NPFC                   ; /* Not-Page &FC - 14A EC           */ 

/***************** OUTPUT PINS *****************************************/
PIN 12  =  !NCS                   ; /* Not-Chip Select                 */ 
PIN 13  =  !OE                    ; /* Not-Output Enable on Read Only  */ 
PIN 19  =  !RNW                   ; /* Low output Read Not Write       */ 

PIN 14  =  !BIN                   ; /* Chip 'B' inhibit latch          */ 
PIN 16  =  !BEN                   ; /* Chip 'B' enable latch           */ 
PIN 17  =  !AIN                   ; /* Chip 'A' inhibit latch          */ 
PIN 18  =  !AEN                   ; /* Chip 'A' enable latch           */ 

/***************** LOGIC EQUATIONS  ************************************/

NCS =	 ERNW                     ; /* Electron R/nW Master CS - 20ROM */


RNW =	!MRNW                     ; /* Master R/nW - 27ROM     	       */	


OE =	!NOE & MRNW               ; /* nOE - 22ROM		       */
This stripped-down code resulted in these 'scope traces:
abr1.jpg
Showing a write followed by a read to the EEPROM
abr2.jpg
Showing the write in more detail
abr3.jpg
Showing a write followed by a read to the EEPROM
I'm not sure why the write signal is different!

The result looked good, however, when in the Master . . . .
IMG_2795.jpg
Trying one of the utilities
IMG_2794.jpg
Results in this - all write operations on the ABR are the same
Tried adding T2 to R/nW:
abr11.jpg
Same result . . . Having a think what to try next!

The only differences I now have, from the modified ARA II, is nCS passes through the DS1210 and all three signals pass through the PLD.

Bridged out the DS1210 - no change! Anyone have any things to try or check?

Note: If I load a valid image into the 28C256 I can read it, save it and use it OK! If I replace the 28C256 with RAM I can read and write to it OK!! So It's just a write issue to the 28C256 . . . I've checked with the data sheet and all write parameters seem to be met!!!

Schematic:
Retro Hardware Battery Backed RAM - 08-09-16.PDF
(241.98 KiB) Downloaded 17 times
Dave H :D

Edits: Just tidying up.
Last edited by daveejhitchins on Sat Aug 11, 2018 1:57 pm, edited 3 times in total.
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by MartinB » Sat Aug 11, 2018 2:43 pm

I’m on hols Dave as you know but quickly, I didn’t ever get my eeprom stuff working in a Master internal socket but everything was fine in a cartridge. That’s probably no help whatsoever but just thought I’d mention it...😜


.
Last edited by MartinB on Sat Aug 11, 2018 2:43 pm, edited 1 time in total.

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Sat Aug 11, 2018 3:36 pm

MartinB wrote:
Sat Aug 11, 2018 2:43 pm
I’m on hols Dave as you know but quickly, I didn’t ever get my eeprom stuff working in a Master internal socket but everything was fine in a cartridge. That’s probably no help whatsoever but just thought I’d mention it...😜
Thanks, Martin . . . I think Steve must have, as I'm sure one or more of his boards uses EEPROM.

I'm going to try T2 with the other signals. The data sheet show a nCE controlled write sequence - so that's next on the list.

Dave H :D
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by MartinB » Sat Aug 11, 2018 8:16 pm

To be honest, I didn't ever do much intelligent investigation into the Master internal eeprom fit - when it wasn't playing ball, I pretty much just retreated to the cartridge solution, not least because there isn't actually that much rom real-estate inside a Master and after all, cartridges are there to be used for just this sort of thing.

Anyway, I was originally just reading-across from the Beeb as shown in blue below but I was getting write issues ('Device is ROM' etc...) and so I later withdrew the blue master details and published the cartridge solution that you linked to.

EEPROM - ok for Beeb, no good for Master.JPG

** Note that the BLUE Master configuration does not work! **

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Sun Aug 12, 2018 1:41 pm

Update . . .

Instigated the nCS controlled write sequence which seems to have fixed the problem.
As in the first post: Top trace down = T2, nCS, Noe and R/nW
abr21.jpg
Second trace from the top, nCS gated with T2 for a nCS controlled write.
abr22.jpg
Close up of the write sequence.
abr23.jpg
Close up of read sequence.
Testing on the Master, with MartinB's utilities, has gone well. The only thing you have to remember is to use the ABR utility UNLOCK before using any of Martin's utilities and LOCK afterwards. Having the software controlled LOCK and UNLOCK means you don't need a physical write-protect switch - bonus :mrgreen:

Now to make sure I haven't broken the Electron side . . .

Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by cmorley » Sun Aug 12, 2018 1:52 pm

daveejhitchins wrote:
Sun Aug 12, 2018 1:41 pm
Having the software controlled LOCK and UNLOCK means you don't need a physical write-protect switch - bonus :mrgreen:
Does this chip return inverse/toggling bytes for a short while after an attempted write even if locked like the Greenliant chips do? That's a problem I had with the chips I used & DFS 2.26 IIRC - tried writing to itself and then next opcode read was incorrect causing a crash.

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Sun Aug 12, 2018 5:17 pm

cmorley wrote:
Sun Aug 12, 2018 1:52 pm
daveejhitchins wrote:
Sun Aug 12, 2018 1:41 pm
Having the software controlled LOCK and UNLOCK means you don't need a physical write-protect switch - bonus :mrgreen:
Does this chip return inverse/toggling bytes for a short while after an attempted write even if locked like the Greenliant chips do? That's a problem I had with the chips I used & DFS 2.26 IIRC - tried writing to itself and then next opcode read was incorrect causing a crash.
Yes it does . . . hence the beauty of the ABR with it's 'lock' as it powers-up in the locked state you don't have any problems.

Just need to persuade Martin to alter his great EEPROM utilities to do this for the Master: Remove ROM from ROM table : Unlock ABR : Load image into ROM : Lock ABR : Read ROM type and insert into ROM table . . . Magic . . . :-

Dave H :D
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Sun Aug 12, 2018 5:27 pm

For completeness, here are the Electron nCS, nOE and R/nW signals for a write and read cycle:
abr_elk1.jpg
Showing Electron write and read cycle
abr_elk2.jpg
Write expanded
abr_elk3.jpg
Read expanded

Code: Select all

And here is the PLD code:
Name     ABR-Issue3 ;
PartNo   16L8 ;
Date     12/08/2018 ;
Revision 03 ;
Designer D.E.J. Hitchins ;
Company  Retro Hardware ;
Assembly Advanced Battery Backed RAM ;
Location IC3 ;
Device   g16v8ma ;
/* *************** Revision History *************************************/
/* 12-08-18 Added T2 to Master nCS (for CS write sequence)              */
/*          Added specific OE for Master                                */
/*          Removed T2 from all R/nW terms                              */
/* *************** INPUT PINS *******************************************/
PIN 1   =  NOE                    ; /* Not-Output Enable                */
PIN 2   =  ERNW                   ; /* Electron Read/Write - Master CS  */
PIN 3   =  QA                     ; /* Page latch LSB                   */
PIN 4   =  A1                     ; /* Address line 1                   */
PIN 5   =  A0                     ; /* Address line 0                   */
PIN 6   =  T2                     ; /* CPU clock phase 2                */
PIN 7   =  A5                     ; /* Address line 5                   */
PIN 8   =  MADET                  ; /* Master detect - Low if Master    */
PIN 9   =  MRNW                   ; /* Master Write - Electron N/U      */
PIN 11  =  NA23467                ; /* Nanded address lines 2,3,4,6 & 7 */
PIN 15  =  NPFC                   ; /* Not Page &FC                     */

/* *************** OUTPUT PINS ******************************************/
PIN 12  = !NCS                    ; /* Not-Chip Select                  */
PIN 13  = !OE                     ; /* Not-Output Enable on Read Only   */
PIN 14  = !BIN                    ; /* Chip 'B' inhibit latch           */
PIN 16  = !BEN                    ; /* Chip 'B' enable latch            */
PIN 17  = !AIN                    ; /* Chip 'A' inhibit latch           */
PIN 18  = !AEN                    ; /* Chip 'A' enable latch            */
PIN 19  = !RNW                    ; /* Low output Read Not-Write        */

/********** Declarations and Intermediate Variable Definitions **********/
FCDC = !NPFC & !A0 & !A1 & !A5 & !NA23467 & T2;     /* Unlock &FCDC     */
FCDD = !NPFC &  A0 & !A1 & !A5 & !NA23467 & T2;     /* Lock   &FCDD     */
FCDE = !NPFC & !A0 &  A1 & !A5 & !NA23467 & T2;     /* Unlock &FCDE     */
FCDF = !NPFC &  A0 &  A1 & !A5 & !NA23467 & T2;     /* Lock   &FCDF     */
/* *************** LOGIC EQUATIONS  *************************************/
NCS =      MADET & !NOE & T2                        /* Electron         */
        # !MADET & ERNW & T2;                       /* Master           */

OE  =      MADET & !NOE & ERNW                      /* Elk nOE on read  */
        # !MADET & !NOE & MRNW;                     /* Mas nOE on read  */

AEN =      MADET & !ERNW & FCDC                     /* Unlock &FCDC 0/1 */
        # !MADET & !MRNW & FCDC
        # !AIN;

AIN =      MADET & !ERNW & FCDD                     /* Lock &FCDD 0/1   */
        # !MADET & !MRNW & FCDD
        # !AEN;

BEN =      MADET & !ERNW & FCDE                     /* Unlock &FCDE 1/3 */
        # !MADET & !MRNW & FCDE
        # !BIN;

BIN =      MADET & !ERNW & FCDF                     /* Lock &FCDF 1/3   */
        # !MADET & !MRNW & FCDF
        # !BEN;

RNW =      MADET & !ERNW & !QA & AEN                /* Write Elk 0/2    */
        #  MADET & !ERNW &  QA & BEN                /* Write Elk 1/3    */
        # !MADET & !MRNW & !QA & AEN                /* Write Mas 0/2    */
        # !MADET & !MRNW &  QA & BEN;               /* Write Mas 1/3    */



/* **********************************************************************/
Dave H :D
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by cmorley » Sun Aug 12, 2018 5:30 pm

daveejhitchins wrote:
Sun Aug 12, 2018 5:17 pm
Just need to persuade Martin to alter his great EEPROM utilities to do this for the Master: Remove ROM from ROM table : Unlock ABR : Load image into ROM : Lock ABR : Read ROM type and insert into ROM table . . . Magic . . . :-

Dave H :D
Sounds like the exact process needed for my B modules... including persuading Martin to add support [-o<

:D

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Sun Aug 12, 2018 6:01 pm

cmorley wrote:
Sun Aug 12, 2018 5:30 pm
Sounds like the exact process needed for my B modules... including persuading Martin to add support [-o<
That would be similar to my AP7
ap7a.jpg
ap7a.jpg (21.89 KiB) Viewed 648 times
ap7b.jpg
ap7b.jpg (16.16 KiB) Viewed 648 times
An ABR for an IC socket - Shown here in an Electron AP6 but you could change the links and it was supplied with leads to fit into a Beeb.

A bit bigger than you offering :-k

Dave H
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by MartinB » Mon Aug 13, 2018 7:45 am

Dave wrote:Just need to persuade Martin to alter his great EEPROM utilities to do this for the Master: Remove ROM from ROM table : Unlock ABR : Load image into ROM : Lock ABR : Read ROM type and insert into ROM table . . . Magic . . . :-
So would that be a new independent utility in the set or a change to *EELOAD or is it something else ? (Being slow on the uptake as usual... :) )

Chris wrote:Sounds like the exact process needed for my B modules... including persuading Martin to add support [-o<
Same question really Chris and not really sure what support for your modules would involve? Would the existing utils work if they supported a different lock/unlock mechanism?

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Mon Aug 13, 2018 7:38 pm

Hi, Martin or is that the invisible man :wink:

I've been using your EEPROM utilities a lot, over the last few days, during the testing of the ABR with a 28C256 fitted, not all the features but enough.

The following are not criticisms but observations: If I follow your instructions to the letter - the most important one being Ctrl/Brk after each command (I'm sure I've seen that somewhere?) then there are no problems. I noted that if I didn't Crtl/Brk e.g. just carried on using the same or another of the utilities, then any follow-on command usually didn't work correctly.

I don't think 'new' versions are needed as what I'm suggesting [-o< wouldn't affect the normal operation e.g. for none ABR 28C256s. I've always wondered about the on-chip locking feature - when used within the Acorn environment - OK it stops the contents from being corrupted but any write protect switch will do the same. Importantly it doesn't stop programs falling over if a write is accidentally issued while relying on reading the contents e.g. the read lock-out.

So, for any utility that 'modifies' the contents: Unlock ABR : Load image into ROM : Read ROM type and insert into ROM table : lock ABR. Of course you'll need to know which machine you're in as the ROM Table and latch are in different places for the Master And electron (more egg sucking lessons later :wink: ).

I’m currently looking at something strange when using a RAM based ABR and an EEPROM based ABE in a Master at the same time. I’m not sure I have the full details, as yet (the dinner gong shout interrupted me!). Two things I'm investigating (1) Programmed a RAM based ABR in an Electron - both positions with the same ABR108 utilities. Fitted it into a Master and a ROMS only showed one. This could be down to the OS just reporting one, however, I’m going to check with ADT to see if the other image is actually there. (2) Even more strange, with the 2 x ABR in position. Both ABRs were empty. I then unlocked them both with UNLOCK #. Then using Martin’s EEP32 UNLOCK 23 util made sure the other lock wasn’t active. Then EELOAD ABR108 0 (the EEPROM ABR was in the back slot) followed by ROMS - it’s then I noticed that the ABR108 was showing up in slot 0 and slot 2 - even after a Ctrl/Brk - Hmmm! Need to look at that tomorrow.

More later - Dave H :D
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by MartinB » Mon Aug 13, 2018 8:36 pm

On the softlock, as soon as I discovered this quaint eeprom feature, it sounded really cool so I just dived straight in and added the tools but this was before I encountered the now notorious ‘write-offline’ quirk that was tending to hang Acorn kit. So, even though I later mandated a hardware write-protect switch to combat the latter, I left the LOCK and UNLOCK features in the utilities because lots of users were still telling me that it worked fine! Personally though, I do recommend the use of a hardware write-protect switch....🤓

On the <Ctrl><Break> thingy, that’s mostly a broad generalisation about modifying any sideways rom configuration simply because many such roms have complex initialisation needs and the OS is easily confused. It could of course also be a bit of lazy programming on my part but things such as *EELOAD do inevitably tend to use main memory as a buffer and that can often then lead to ‘Bad program’ messages and the like.

Anyway, I do think that the utilities could probably benefit from another overhaul in light of your experiences, suggestions and comments and it would be good to embrace Chis’s modules in a one-for-all package. I guess as ever though, finding the bandwidth will be the governor.... :|

On your last ‘issue’, I shall await further info because I haven’t a clue what you’re on about.... :lol:


.
Last edited by MartinB on Mon Aug 13, 2018 8:49 pm, edited 1 time in total.

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Tue Aug 14, 2018 6:38 am

MartinB wrote:
Mon Aug 13, 2018 8:36 pm
On your last ‘issue’, I shall await further info because I haven’t a clue what you’re on about.... :lol:
I feel a few videos are needed - just in case my imagination has gone astray . . . :shock:

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Wed Aug 15, 2018 5:26 pm

More testing has revealed a possible faulty Master. Need to do some more testing tomorrow morning. For the first hour or so of use I'm getting some strange results (see images and attached videos). Then it starts to behave. So I've been fighting these faults and no faults trying to get an EEPROM based ABR to work. More later on this . . .
IMG_2822.jpg
No way this could ever happen!!
The first vid show a RAM based ABR being tested and loaded with the ABR utilities using an Electron. The second vid shows the loaded ABR, in a Master, with a ROMS listing. The real interesting bit is not just that one of the images has been removed but it's been filled with zeros! If I return the ABR to the Electron it has really been wiped, despite the active-at-power-up write protection . . .
Master Playing-up.zip
(774.53 KiB) Downloaded 6 times
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by MartinB » Wed Aug 15, 2018 6:17 pm

What makes you sure that both images have been loaded on the Elk in the first place? Your video shows the program asking to load the ABR and then showing slots 2 & 3 with the ABR utils but do you actually check off-video that each has the image physically loaded? I’m guessing that one of the two slots (3) is already full of zeroes before it leaves the Elk.... :-k


Lots of edits because that’s how my mind works. I grow to hate this edits footer change more each day..... :x
Last edited by MartinB on Wed Aug 15, 2018 6:20 pm, edited 3 times in total.

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Wed Aug 15, 2018 6:50 pm

MartinB wrote:
Wed Aug 15, 2018 6:17 pm
What makes you sure that both images have been loaded on the Elk in the first place? Your video shows the program asking to load the ABR and then showing slots 2 & 3 with the ABR utils but do you actually check off-video that each has the image physically loaded? I’m guessing that one of the two slots (3) is already full of zeroes before it leaves the Elk.... :-k
I asked myself the same question . . . So I tried the recently loaded ABR in a second Electron/Plus 1 and then had a peek with ADT - Yup! Two images . . . Next?

Dave H :D
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by MartinB » Wed Aug 15, 2018 7:00 pm

Could you repeat but load a different image into each slot so that the two slots aren’t the same. Include the second Elk confirmation before moving to a Master.

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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Wed Aug 15, 2018 7:13 pm

MartinB wrote:
Wed Aug 15, 2018 7:00 pm
Could you repeat but load a different image into each slot so that the two slots aren’t the same. Include the second Elk confirmation before moving to a Master.
Yup! Tried that - I've actually been trying different 'ideas' for the last two days - and repeating the same tests over and over. As time went by everything started to work, so I had to go back in the test sequence to try and figure what made it work - finally realising it wasn't anything I'd done. This morning I started the testing again - failures - so left the Master switched on for over an hour - everything working. I'll repeat the process again tomorrow, just to make sure.

Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
Products: ARA II, ARA III, ABR, ATI, AP6, MGC, AP5 . . .
For a price list, contact me at: Retro Hardware AT dave ej hitchins DOT plus DOT com

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Elminster
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by Elminster » Wed Aug 15, 2018 8:08 pm

Pixies. I am sure it is pixies, i often get odd problems. I believe it is a pixie conspiracy to drive me mad.

I started using spreadsheet to track things i have tried 9on my video issue) as I started to find I was going around in circles.

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daveejhitchins
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Re: Converting ABR to EEPROM (28C256) for the Master

Post by daveejhitchins » Fri Aug 24, 2018 7:33 am

Lots more testing carried out to find out what's been going on with my Master. I started to have crashes/freezes, just to add to the mix of other ABR problems. Decided to look-inside :shock: Just a few socketed IC, but reseated them anyway - Hmmm! Crashing/freezing problem gone :D Still had original ABR issues e.g.
IMG_2825.jpg
So, I need to look at that in the near future . . .

I'm happy that the PLD code here is good - so, if anyone wants their ABR PLD reprogramming, to accept 28C256 EEPROMs, just let me know and I'll sort them out for you.

As a result of all the testing I've done, I've managed to complete a project for Arcadian: a board to host one or two ROM images fitted in an Acorn case for show gaming use. I'll also make it available here - project code ARA III. It will consist of a PCB, case (if required) two ICs and a jumper. The jumper is for write protection (could link to an eternal switch). It's effectively a low cost writable (by fitting the link) ROM board that works in either the Master or Electron - writable in either machine. More later - I'll add a link here when I gather further information.

Dave H :D

Edit: I forgot to add something else that I've discovered during all the testing:

Whilst doing the testing I decided I needed to know the Lock status of the ABR under test. So I added two three legged bi-coloured LEDs. So, I can confirm that the ABR is always locked at power-up. The Electron Plus 1 Support ROM works correctly, using U & L inthe appropriate places, however, I've discovered an undocumented 'feature' in the original ABR Utilities!

Although not appearing in the User Guide, I always thought that the LOADROM command did the following:
Example: *LOADROM <filename> <ROM#> - ABR would be Unlocked, file would be written and ABR would be Locked.

Well, almost right: ABR is Unlocked, file is written BUT ABR in NOT Locked UNLESS you add L to the end of the command!

I've now updated the User Guide to read:

***************************************************************************
LoadROM

This program is used to load a RAM bank with an image stored on the current filing system.

*LOADROM <filename> (<bank>) (L)
Or from TAPE
*/LOADROM <filename> (<bank>) (L)

Bank number is optional, but must be in hexadecimal if present. If no bank number is given the program will test each bank, working down from bank F to find ones which are RAM. If the bank is occupied it will ask if you want to overwrite the image currently loaded into it. If the bank, is empty the image will be loaded into it. If the bank number specified is already in use you will also be asked whether you want the present occupant overwritten. ‘L’ is optional and, when used, Locks the ABR/ATI after the file has been loaded.
***************************************************************************
Last edited by daveejhitchins on Fri Aug 24, 2018 7:49 am, edited 1 time in total.
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
Products: ARA II, ARA III, ABR, ATI, AP6, MGC, AP5 . . .
For a price list, contact me at: Retro Hardware AT dave ej hitchins DOT plus DOT com

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