Testing all 4 Ports on the New AP5

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daveejhitchins
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Testing all 4 Ports on the New AP5

Post by daveejhitchins » Thu Mar 15, 2018 3:49 pm

Up to now I've been testing individual AP5s as a one-off. But now I have more than a few to test!

I've read 1024MAK's interesting thread here, and have modified it to test both A and B ports - works well.

I've also added some more BASIC to test the actual read and write functions, both ways, between the two ports using a 'data only' cable between them. Yesterday, when testing this, it was very intermittent e.g. I was seeing what I think were read errors - I monitored the output, with the 'scope and they looked OK. Today it works fine . . . Any ideas? Can anyone think of any other tests I can implement with just this cable? Or maybe some simple circuit?

For the 1MHz BUS I just plug in the BeebCSImini - I have the User Port test software on there. For the Tube interface I use my DE0-Nano but currently just plug it in and check the Start-up screen - Would be good to have something load and run from there - suggestions?

I also plug-in 2 x ROM to test their functionally. Currently unable to test ROM 13 as I'm using a version 1 AP6 that doesn't let me isolate it's socket 13 :?

Dave H :D
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Re: Testing all 4 Ports on the New AP5

Post by CMcDougall » Thu Mar 15, 2018 7:48 pm

I've been playing with my lot too, yes intermittent is very true, not just your great AP5!

I think the elk likes to be off 30mins in between test sections, thats all of them, ie Issues 2, 4 & 6 :shock:

Add ons to Plus1 usually work on first go of day, then go pear shaped after a few games :? *FX200,3 then Break has no effect [-( :-k ](*,)
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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Thu Mar 15, 2018 7:56 pm

daveejhitchins wrote:I've also added some more BASIC to test the actual read and write functions, both ways, between the two ports using a 'data only' cable between them. Yesterday, when testing this, it was very intermittent e.g. I was seeing what I think were read errors - I monitored the output, with the 'scope and they looked OK. Today it works fine . . . Any ideas? Can anyone think of any other tests I can implement with just this cable? Or maybe some simple circuit?
Some more testing today . . . As Col. suggested: Worked just fine for maybe a hour - then started with the errors again. May have to get the Logic Analyzer on the job and 'see' what the data actually looks like.

Dave H :D
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Re: Testing all 4 Ports on the New AP5

Post by hoglet » Fri Mar 16, 2018 12:52 pm

Hi Dave,
daveejhitchins wrote: Some more testing today . . . As Col. suggested: Worked just fine for maybe a hour - then started with the errors again. May have to get the Logic Analyzer on the job and 'see' what the data actually looks like.
If you could post you test programs and details of the Port A <===> Port B cable I'll try to replicated this as well.

Are you noticing any unreliability on the 1MHZ Bus or Tube ports, or is it just the 6522 ports?

Dave

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Re: Testing all 4 Ports on the New AP5

Post by MartinB » Fri Mar 16, 2018 5:50 pm

Dave H - I also did this on EUP......
EUP fast transition test.JPG

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Re: Testing all 4 Ports on the New AP5

Post by CMcDougall » Fri Mar 16, 2018 6:36 pm

^ I used many different types of 6522s, you think it's fixed, switch off for 30+mins.... same errs again :shock:
even tried rom in different positions, also cart in different plus1 slots 01/23, seemed to work, then 30mins... same again :?
weirdness happens even when programming EEPROMS 32k, with UPURS , ATI/ABR & AP5, thinking my eeproms were popped, put in another cart, fine again...
The Slogger Plus2 is much worse for user port MMC , now you see me, now you don't :lol:

Was there not a mention of this in an advert BITD also, saying they did not know either, so that eliminates old chips / resistors / caps etc 8)
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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Fri Mar 16, 2018 7:04 pm

MartinB wrote:Dave H - I also did this on EUP......
Thanks Martin, I'll give that a go. I have made some progress! 1024MAK's code worked* a treat, so couldn't understand why I was seeing so many problems. Than I realised Mark was Writing and reading back to back - where I had a procedure for write and read . . . and it makes a BIG difference!

I've almost got the 'test' working - just some final debugging to do.

*I've see continuous first byte corruption - just on port A ? I try testing Port B first and see what that produces.

More later. . .

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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Fri Mar 16, 2018 7:07 pm

@Col. . . .

I'm hoping it's just my programming and lack of understanding of the 6522!

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Re: Testing all 4 Ports on the New AP5

Post by CMcDougall » Fri Mar 16, 2018 8:58 pm

daveejhitchins wrote: understanding of the 6522!
hi Dave, think this may be answer to always different:
hoglet wrote:more testing with the different 6522s, and it does seems that all are susceptible to a greater or lesser extent. They also seem much more susceptible when cold than when hot. With one of them (the SY6522), once the system has been running for a couple of minutes, it seems reliable. Because of this temperature induced variation, it's actually quite hard to be definitive about whether a given change had made a positive difference or not
taken from the Mk2 blue EUP sale thread bottom pg2 :shock:
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Re: Testing all 4 Ports on the New AP5

Post by hoglet » Fri Mar 16, 2018 9:09 pm

daveejhitchins wrote: I'm hoping it's just my programming and lack of understanding of the 6522!
Can you post a listing of your test program?

I would have thought any 6522 unreliability would have shown up pretty quickly in testing MMFS. I've not had any problems at all.

Dave

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Re: Testing all 4 Ports on the New AP5

Post by MartinB » Fri Mar 16, 2018 9:20 pm

taken from the Mk2 blue EUP sale thread bottom pg2 :shock:
To be fair, Dave (hoglet) was referring there to the susceptibility of a given 6522 in edge-case circumstances to very short duration clock glitches, such as the one that my EUP clock regeneration circuit can cause when generating a 1MHz clock from the 16MHz source. I’ve never experienced any functional problems with this myself (and I did know about it, I described it early on in the EUP development thread) but Dave attributed an occasional MMC corruption to the glitch (or similar, can’t quite remember the details without re-reading?) with certain versions of 6522. Soooo.... fair comment Col but unrelated here I think 8)

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Re: Testing all 4 Ports on the New AP5

Post by 1024MAK » Fri Mar 16, 2018 10:19 pm

Is it a problem wirh port A or port B?

Only there are differences between the two.

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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 7:56 am

hoglet wrote:Can you post a listing of your test program?
Just taken this snapshot of the Read/Write section - The rest of the program is just displaying the data formatted.
IMG_2214.jpg
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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 8:11 am

1024MAK wrote:Is it a problem with port A or port B?
When I first ran the program, this morning, it was OK - after a few minutes this is what I see. The only modification to your program was to duplicate the procedure to test the second port.
IMG_2215.jpg
Note: As I hadn't finalised 'my' program I haven't tried another 6522.

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Re: Testing all 4 Ports on the New AP5

Post by MartinB » Sat Mar 17, 2018 8:25 am

In Mark's code....

10 ?&FE62=&FF :REM Set user port to output
20 PROCOUTPUT(&FF,"ALL ON")
30 PROCOUTPUT(&00,"ALL OFF")
40 PROCOUTPUT(&AA,"HALF ON")
50 PROCOUTPUT(&55,"OTHER HALF")
100 GOTO 20
500 DEF PROCOUTPUT(X%,A$)
510 ?&FE60=X%
520 PRINT A$," Output=";~X%," Input=",~?&FE60
530 FOR L=0 TO 3000:NEXT
540 ENDPROC

...I think that the in and out displayed values are actually reversed presuming 'Input' means the value being poked to the port....

520 PRINT A$," Input=";~X%," Output=",~?&FE60

Though that doesn't actually affect a working result and isn't your problem. What I suspect your are doing Dave is not correctly changing the values from B to A. You need to have &FE61 in lines 510 and line 520 with &FE63 in line 10. Are you doing all three?

EDIT : Just corrected that!

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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 8:41 am

Just ran Mark's (modified) code again - Passed first run - failed, as photo above ^^, second run - my modified code below:
IMG_2217.jpg
IMG_2216.jpg
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Re: Testing all 4 Ports on the New AP5

Post by MartinB » Sat Mar 17, 2018 8:43 am

Did you see that I corrected myself a few minutes after posting? There are three changes of &FExx numbers? (plus the printed result i/o swap...)

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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 8:50 am

Ah! I think that the in and out displayed values are actually reversed presuming 'Input' means the value being poked to the port....
I Read it as the Output was 'to' the 6522 and the Input was 'from' the 6522 . . .

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Re: Testing all 4 Ports on the New AP5

Post by MartinB » Sat Mar 17, 2018 9:05 am

I read it as i/o from the perspective of the 6522 but anyway, it's just semantics 8)

So are you definitely making the other three changes when switching between Port A and Port B tests? If so, then you clearly have some fundamental problem there.... :?

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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 10:02 am

More testing:
1) Mark's code (my version):
When I first run the test it passes . . . If I run the test a second time e.g. when it completes I just enter RUN - it fails and will continue to fail until I Ctrl Brk OLD RUN - then it passes again, on the first run only. It also continues to fail if I replace the END statement with GOTO 10

2) My code:
Not quite the same as above - I have replaced END with GOTO 10, as above. It's happily cycling through the code and passing every time. If it fails, however, it will always fail until Crtl Brk OLD RUN . . .

I'm next going to change: first the Electron (this one has Prime's MRB fitted) and then, if no better the Plus 1 (this has a V1 AP6 fitted. Thereafter, depending on the results, a different 6522 and then different AP6 etc. etc.

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Re: Testing all 4 Ports on the New AP5

Post by hoglet » Sat Mar 17, 2018 10:16 am

Dave,

I've not yet been able to reproduce this failure - which looks like lost (or misdirected) writes.

I'm going to leave a soak test running for the next few hours.

Can you confirm a few things about the failing system:
- What issue Electron is it?
- What exact type of 6502 is fitted?
- What exact type of 6522 is fitted?
- Are you running with the MRB enabled or disabled? Do both fail?
- Are you running the latest version of the CPLD design (PRINT ~?&FCD7 should return 94)
- Is the FOR/NEXT delay loop significant? Do you still see failures if this is removed?

Dave

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Re: Testing all 4 Ports on the New AP5

Post by 1024MAK » Sat Mar 17, 2018 11:37 am

I don't know about on the Elk, but on the Beeb, the OS may change the 6522 VIA settings in some circumstances.
Hence the control registers have to be set up each time the program is run.

If one of the registers is not specifically set by the program, you are relying on the setting last used, or after a power on / reset, the setting that the OS set the chip to use.

Mark
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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 11:44 am

- What issue Electron is it?
It's an Issue 1 - German with the latest ULA. Changing the Electron makes no difference.

- What exact type of 6502 is fitted?
R6502AP/R6502-13 - via my Chinese supplier - Changing to a UMC (old stock from the 80's) makes no difference.

- What exact type of 6522 is fitted?
R6522AP/R6522-40 - These come via my Chinese supplier - Changing, to another from a different tube, doesn't change the results.

- Are you running with the MRB enabled or disabled? Do both fail?
I run with shadow enabled, however, turning the MRB off, with the switch, still produces the fault (Mark's Test)

- Are you running the latest version of the CPLD design (PRINT ~?&FCD7 should return 94)
Hmm! I'm not, on this AP5 (returns 93), which was built some time ago! I believe all recent ones are OK - Latest batch return 94 - no difference to the test. Note: it's Port A that is failing on Mark's test.

- Is the FOR/NEXT delay loop significant? Do you still see failures if this is removed?
Removing or shortening the loop makes no difference.

Different Plus 1 (with standard Plus 1 support ROM), no difference . . .
But . . . My test is still working and the first 2 tests are 'similar' to Mark's test - I cycle through 0 to 255 whereas Mark just uses 0, 55, AA, FF.

OK What's next?

Dave H :D
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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 11:45 am

1024MAK wrote:I don't know about on the Elk, but on the Beeb, the OS may change the 6522 VIA settings in some circumstances.
Hence the control registers have to be set up each time the program is run.

If one of the registers is not specifically set by the program, you are relying on the setting last used, or after a power on / reset, the setting that the OS set the chip to use.
The Electron OS doesn't 'know' about the 6522, however, I do set-up the 6522 every time I write/read to it.

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Re: Testing all 4 Ports on the New AP5

Post by 1024MAK » Sat Mar 17, 2018 11:58 am

Dave, in case I have missed it, what (if anything) is connected to the port A pins?

Mark
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Re: Testing all 4 Ports on the New AP5

Post by hoglet » Sat Mar 17, 2018 12:04 pm

daveejhitchins wrote: But . . . My test is still working and the first 2 tests are 'similar' to Mark's test - I cycle through 0 to 255 whereas Mark just uses 0, 55, AA, FF.

OK What's next?
Sorry if you have posted this already, but just so I am running 100% the same test code, can you re-post the listing of the test that is failing.

What other ROMs are present in your Elk?

I've had the test looping now for over 10,000 iterations without any failure (I added a check of the result).

Dave

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Re: Testing all 4 Ports on the New AP5

Post by hoglet » Sat Mar 17, 2018 12:21 pm

Dave,

When you are running this test, do you have a cable connecting the data pins on Port A to the data pins on Port B?

If so, then that is the cause of the failures.

Try running the test with this cable removed.

Dave

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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 12:46 pm

@Dave
What (if anything) do you have attached to the 1MHz Bus and Tube Ports when the failure happens?
1MHz Bus has the BeebSCSImini attached - That's how I'm loading and saving the code. Nothing on the Tube connector. No other ROMs fitted to the AP5, i do have other ROMs in my AP6, however, I've tried with a different Plus 1 with no AP6 fitted and had the same results.

Mark's modified test is here. Sorry, it's a type-in!

@Mark
I have a ribbon cable running between the two ports with just the Data lines connected - which has just prompted me to test without the cable - and it clears the fault!! Which is strange as my test, which is similar (here) to yours but cycles through 0>255 is working OK now, with the cable - Very strange . . . Perhaps because I set-up the output every time? I'll try and report back.

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Re: Testing all 4 Ports on the New AP5

Post by 1024MAK » Sat Mar 17, 2018 12:48 pm

6522 VIA
Port A

Normally (input latching disabled) reading the port results in the actual logic levels on the pins being transferred to the data bus.

Port B
This is similar, but in output mode, a read will return the logic level for that bit that is stored in the output latch. Not the actual logic value on the pin.

Output loading of port pins
Because port B returns latched data, it will return the value of the last written data.
However, port A will report the current state of the logic levels on the pins. This may not be the value that was last output to the pins if an external circuit is loading the pins. For example, a pin set to logic high (1) may have the output voltage dragged down below the logic threshold, hence when read, it shows as a logic low (0).

So if you have ports A and B connected together, one port should be set to input mode in the DDR.

Oh, and port B outputs are stronger than port A outputs,so if a port A pin and a port B pin are connected together and both are set as outputs, I would expect port B to 'win'.

Mark
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Re: Testing all 4 Ports on the New AP5

Post by daveejhitchins » Sat Mar 17, 2018 12:58 pm

@Mark
Perhaps because I set-up the output every time? I'll try and report back. It doesn't make any difference.

And from your last post: I thought it might be a case of me not-quite-understanding-the-6522. Still strange though, that my test is now working!

OK, moving on . . . Could I use one of the control pins to latch-out from Port B and Latch-in to Port A ? As I suspect I may still have a problem that will probably bite-me later :shock:

Dave H :D
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