I'm sure Ian will correct me if I get anything wrong here (I've not tried one of his buffer boards myself yet).*STEVE wrote: ↑Mon Jun 22, 2020 2:12 amSo, I've built one up using parts I had available, the XC9572XL dev board in the original jumper-wired version and proto-board, but to the latest spec schematic (rgb-to-hdmi.shc and using the front-end from the three-bit-buffer (buffer.sch). I've programmed the CPLD sucessfully (to the newer 6-bit version since i've built wired this up to the 6-bit schematic) but am seeing two things when it boots. One, it's saying 'no sync detected' although there is on the SYNC line (buffered through the 74LS08) and the interface is stuck at '6 BIT RGB', although I think this should reflect 3-BIT TTL.
I suspect this is just a wiring error and the PI thinks I'm using the 6 bit analogue interface when I want to use the 3-Bit TTL.. Q1: how is the interface type detected?
I think all the detection is working correctly, and an interface type of 6_BIT_RGB is what I would expect.
The software needs to detect the presence of the analog interface, because it contains DACs that need programming over an SPI interface. It does this by looking at the level on the DETECT signal (CPLD pin 19). This is pulled down on the CPLD board by a weak (10K) pulldown, and pulled up on the analog board by a stronger (1K) pullup. So when the analog interface is fitted, DETECT is read back as high.
However, I your case you have effectively built one of the buffer boards, which is entirely transparent to the software.
In this case, the "Interface" value shown by the software simply reflects the CPLD design programmed, and as you have programmed the 6-bit RGB CPLD, it's showing up as "6 BIT RGB". This is exactly what I would expect, so I think the problem lies elsewhere.
I also should say the the 6-bit RGB CPLD is capable of handling both 3-bit and 6-bit inputs, so it's the right version to have programmed.
This sounds right to me.
The wiring details for various systems are detailed here:
What type of computer system are you trying to connect?
What profile have you selected?
I think the most likely scenario is you have a wiring error somewhere relating to SYNC.
The composite sync signal should go to pin 23 of the CPLD (marked SYNC). You should also then see CSYNC come back out of the CPLD on pin 20, which should connect to GPIO23 on the Pi.
Can you try to follow this through all the way to the Pi?
Can you post a couple of photos of your construction?
Not really, they just provide a small amount of termination.
In fact, if it's a Beeb that is driving this interface, that's quite a low impedence source, so you might benefit from much lower value resistors (e.g. 220R). But all the original versions of the design didn't have any termimation at all, and worked fine.