Code: Select all
lda #$81 ; DB38 A9 81 .. sta LFEE0 ; DB3A 8D E0 FE ... lda LFEE0 ; DB3D AD E0 FE ... ror a ; DB40 6A j bcc LDB4D ; DB41 90 0A .. ldx #$FF ; DB43 A2 FF .. jsr mos_Pass_service_commands_to_sideways_Roms; DB45 20 68 F1 h. bne LDB4D ; DB48 D0 03 .. dec sysvar_TUBE_PRESENT ; DB4A CE 7A 02 .z. LDB4D: ldy #$0E ; DB4D A0 0E ..
Unfortunately this is problematic as I will be attaching the cpu via a cpld and a level shifter chip the bus will not float in this (rather horrible) way.
So, I need to come up with a way to defeat this on the Model A/B (not sure about B+) my initial tests on the master seem to indicate that the master bus is pulled up to FF anyway?
In Hoglet's AtomBusMon there is a setting to fake $FE whenever tube is read and this must be turned on / off when compiling the vhdl. I could do this with a jumper on the board but this would require a chunk of CPLD space which is becoming a limited resource. That would mean changing the jumper depending on whether you want the tube to run or not - not great, though maybe an external switch?
I could include a patched OS1.20 with a different test: i.e. set the bit to 0 to indicate presence!
Use a 74LVC4245 buffer instead of a 74CB3T2611 - that would push up cost and board size as I'd need more chips and also take more CPLD space as the 2611 doesn't require extra signalling for directionality
So, questions are:
- is this limited to Model A/B or does it happen on Elk, B+, Master/Compact etc?
- what is the preferred method
- what have I missed?