Myelin's in-system updateable MegaROM for the BBC Master 128

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Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Fri Nov 10, 2017 10:31 pm

Another batch of Acorn hardware projects incoming... here's the first: the updateable master megarom, a replacement for the Master 128's MOS ROM, that can be reprogrammed by an attached microcontroller while the machine is running. The idea here is to make it easy to use and update ROM software in a Master 128, without having to use cartridges for everything. Especially convenient if you work on software like MMFS that cross-compiles from a different machine, as it'll allow you to flash your code into the chip directly from the machine you're building on.

The board has a CPLD and a 128KB-512KB flash chip (SST39SF010/020/040), and goes in the Master 128's MOS ROM socket. It has a header that can connect to a microcontroller for flash programming, and a header to go to a pair of switches, if you want to be able to switch operating systems on the fly, like with one of RetroClinic's DualOS/MultiOS boards.

The PCBs just arrived in the mail, and I should have all tested sometime in the next couple of weeks. Watch this space :)
megarom_front.jpg
It's open source (Apache 2.0 license) like all my other Acorn hardware, and the latest designs live on GitHub here: https://github.com/google/myelin-acorn- ... le_megarom
Last edited by myelin on Tue Jan 30, 2018 11:15 pm, edited 1 time in total.
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Re: An in-system updateable MegaROM for the BBC Master 128

Post by danielj » Sat Nov 11, 2017 5:00 am

That is fab! Loving your work :D

d

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Re: An in-system updateable MegaROM for the BBC Master 128

Post by flaxcottage » Sat Nov 11, 2017 9:03 am

Wonderful idea.
- John

Why do I keep collecting Acorn gear? I'm going to need a considerably bigger man-cave. :?

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Wed Feb 14, 2018 6:53 pm

An update on this one... I forgot about it for a while, but over the last couple of weeks have been working on the Verilog and C code to bring it to life. I haven't tested it in an actual machine yet, but am able to program and read the flash over the SPI connection now, which is the hard part. I'll push the code and bitstreams up to GitHub in the next few days.

I have about 5-6 of these boards looking for good homes -- PM me your address and I'll post you a bare board for free. The hardest part to assemble is the 64 pin (0.5mm pitch) XC9572XL-VQG64, which is tricky, but possible to do by hand.
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Wed Feb 14, 2018 7:30 pm

Which way around does it plug in? It looks like it will either clash with my network card or clash with my GoMMC.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Wed Feb 14, 2018 7:57 pm

jgharston wrote:Which way around does it plug in? It looks like it will either clash with my network card or clash with my GoMMC.
It plugs in to IC24 and extends out over IC37 (away from the Econet module). I've confirmed that it doesn't clash with a standard Econet module, but I haven't checked if it clashes with a normal-height ROM in IC37.

If you have the GoMMC in IC27 (the middle of the three ROM sockets), it may fit, although I can't tell from the picture on http://www.zeridajh.org/hardware/gommc/ how far 'north' the GoMMC board extends. I designed this board to end pretty much exactly in between IC27 and IC37, so it might fit or they might *just* clash.
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Wed Feb 14, 2018 8:35 pm

My GoMMC is in the socket next to the MOS ROM as it needs to be in a 32K socket, so it will bmp into it. However, a couple or three IC sockets used as raisers may rise it high enough to overlap the GoMMC.

While I've got my lid off, I may as well take a photo. :)

Hmmm.... there's a thought. Where's the video ULA in a Master? Will the nULA fit in without fouling anything?

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Wed Feb 14, 2018 8:43 pm

DualOS and GoMMC just don't quite fit together. I was wondering if there was some way of shaving the side of an IC header down a bit.

Image

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Wed Feb 14, 2018 9:18 pm

jgharston wrote:DualOS and GoMMC just don't quite fit together. I was wondering if there was some way of shaving the side of an IC header down a bit.
Hm, so the GoMMC really does stick out a bit too far. Interesting to see the placement of the cartridge slots too... I only have a Master 128 motherboard, not a full system in a case, and I didn't realize that the cartridge housing butts right up against the southernmost ROM socket. I could make a riser board that shifts the GoMMC a bit to the south, but then it would clash with the cartridge housing.
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by tricky » Wed Feb 14, 2018 10:31 pm

If the blue thing was in a riser with long legs, would the extra couple of mm be enough?

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by atcurtis » Thu Feb 15, 2018 10:01 am

jgharston wrote:Hmmm.... there's a thought. Where's the video ULA in a Master? Will the nULA fit in without fouling anything?
The Video ULA is kinda under where the internal TUBE board is positioned.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by danielj » Thu Feb 15, 2018 10:43 am

I can safely say it fits without getting in the way of anything in mine, which has MultiOS, Econet and 80186 inside it...

d.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Thu Feb 15, 2018 1:41 pm

danielj wrote:I can safely say it fits without getting in the way of anything in mine, which has MultiOS, Econet and 80186 inside it...
Wonderful. Just need somebody to unsolder my VULA and socket it.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by RobC » Thu Feb 15, 2018 2:47 pm

jgharston wrote: Just need somebody to unsolder my VULA and socket it.
I'll to do it if you're happy to cover P&P. Royal Mail charge £4.40 each way for 1st class/signed for if you just send the PCB in cardboard and bubble wrap...

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Fri Feb 16, 2018 9:59 am

So... I just got a chance to try this out in some real hardware, and the results are pretty puzzling. The in-circuit programming part of the system seems to not be working at all; when I take over the address bus on the flash chip (by getting my CPLD to stop buffering the address signal from IC20, and instead pass in addresses received over SPI from my microcontroller) and perform the chip identification sequence (write AA to 5555, then 55 to 2AAA, then 90 to 5555, then read locations 0 and 1), I get bogus results that change every time, AND I see snow on the screen.

I got really excited for a while after scoping up pin 20 and finding that it was being driven, but then I realized I was actually looking at pin 22 (A16), so that was a red herring. Pin 20 appears to be tied to 5V rather than ground, but the multimeter read 0 ohms, so I guess it's actually tied.

WIth any luck it's just an issue in my Verilog... back to the testbench to see if I can smoke it out!
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Wed Feb 21, 2018 6:37 pm

Good news! Last night I got it all working. It looks like there must have been some kind of grounding issue once I plugged the board into an actual Master 128; I solved it with some tweaks to the Verilog that made it a bit more noise tolerant. Now I can read and write the flash while the machine is running, and it works as expected -- crashes the machine if you take away its ROM when it's running normally, but if you're running entirely out of RAM at the time, all goes well.

I've pushed the Verilog HDL, AVR code, and latest tools to http://myelin.nz/acorn/megarom for your enjoyment :)

I'd say we're at the point now where it's safe for others to start soldering up their boards. I have a few spare boards here too if anyone wants one -- drop me a PM!
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Wed Feb 21, 2018 7:45 pm

RobC wrote:
jgharston wrote: Just need somebody to unsolder my VULA and socket it.
I'll to do it if you're happy to cover P&P. Royal Mail charge £4.40 each way for 1st class/signed for if you just send the PCB in cardboard and bubble wrap...
Actually, I'm tempted to put it in my Compact, where - if I can work out which IC it is - I think is actually socketed already.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Wed Feb 21, 2018 7:51 pm

jgharston wrote:
RobC wrote:
jgharston wrote: Just need somebody to unsolder my VULA and socket it.
I'll to do it if you're happy to cover P&P. Royal Mail charge £4.40 each way for 1st class/signed for if you just send the PCB in cardboard and bubble wrap...
Actually, I'm tempted to put it in my Compact, where - if I can work out which IC it is - I think is actually socketed already.
Ah poo! IC 16, which is soldered in, and the network header is in the way to plug the nULA in. :( (see here)

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by Coeus » Wed Feb 21, 2018 11:02 pm

jgharston wrote:Ah poo! IC 16, which is soldered in, and the network header is in the way to plug the nULA in. :( (see here)
But you could do the OS? I am assuming that is the ROM with label on at the far south east.

Interesting to look at that board - four gate arrays in place of the glue logic of the BBC but where is the RAM? Is it the set of 4 18pin chips at the south end of the board in the middle with what looks like a captital T as part of the marking?

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by jgharston » Sun Feb 25, 2018 11:01 pm

Coeus wrote:
jgharston wrote:Ah poo! IC 16, which is soldered in, and the network header is in the way to plug the nULA in. :( (see here)
But you could do the OS? I am assuming that is the ROM with label on at the far south east.
What do you mean "do the MOS"?
Coeus wrote:Interesting to look at that board - four gate arrays in place of the glue logic of the BBC but where is the RAM? Is it the set of 4 18pin chips at the south end of the board in the middle with what looks like a captital T as part of the marking?
The RAM is the four dark black (!) ICs between the ICs labelled PHILIPPINES. The bottom one you can make out is labelled IC47.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Fri Mar 16, 2018 12:16 am

An update on this project: I have it working reliably in a Master 128, after adding series resistors in the SPI clock and slave select lines, and I've also gotten it working on a Model B, with some modifications.

The solution I thought I'd found (mentioned a few posts up) turned out not to be as reliable as I thought; the failures intermittently came back. I eventually figured out that adding series resistors in the SCK and SS lines got it working nicely. So the original application here, making it possible to update a Master 128 MOS ROM while the machine was running, is working well.

I realized I could also use this to provide 8 flash banks on a Model B; it requires some modifications to the PCB (cutting two pins, soldering wires to the BBC's bank select latch, and soldering jumpers for the /CS lines on the two ROM sockets). I spent most of yesterday evening getting this working in practice.

The most difficult part was getting the BBC to let go of the data bus for long enough to update the flash chip. Holding BREAK wouldn't do it, because it presumably halted the chip while reading RAM. CALL &8038 to execute a halt (undocumented -- "KIL", 0x02) instruction with the address bus pointing at my flash chip (after I flashed BASIC into it) didn't work either, which I'm puzzled about. CALL &8038 followed by holding down BREAK *did* work, however. If anyone can explain to me how the 'KIL' instruction doesn't free up the 6502 data bus, I'd be very curious to hear!
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by crj » Fri Mar 16, 2018 4:08 am

Hmm. What do you mean by "let go" of the data bus? The 6502 has no concept of not accessing memory; every cycle loads or stores something.

In the Master, you're OK, because the bus from the OS ROM is unidirectional to the the memory control ULA and nothing else. A BBC Micro ROM is directly on the processor's data bus, which by my reckoning will only ever be undriven when you load from a memory-mapped I/O location or paged ROM that isn't present?

You've now got me curious to know precisely what happens during reset. The datasheet says of ~RST "during the time that this line is held low, writing to or from the microprocessor is inhibited" without giving any clue what on earth that means for a bus that can't idle. It might be time to bring out the logic analyser.

I fear your plight may be even worse if you plug into one of the other ROM sockets on a Master (or in a cartridge), by the way: so far as I can see, that doesn't even have a buffer isolating the memory subsystem from the CPU bus during the Video ULA's half of each 2MHz cycle!

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Fri Mar 16, 2018 7:33 am

crj wrote:Hmm. What do you mean by "let go" of the data bus? The 6502 has no concept of not accessing memory; every cycle loads or stores something.
By "let go of the data bus", I mean I want the D0-7 lines tristated for about 20 seconds.
In the Master, you're OK, because the bus from the OS ROM is unidirectional to the the memory control ULA and nothing else. A BBC Micro ROM is directly on the processor's data bus, which by my reckoning will only ever be undriven when you load from a memory-mapped I/O location or paged ROM that isn't present?
Exactly. So I need a way to get the CPU to issue continuous reads from memory-mapped I/O locations or paged ROMs that aren't present :) The latter is easier, because my board acts as a paged ROM. Holding the CPU in reset while it's accessing an unmapped paged ROM location is the solution I've got right now, but it would be nice if I could do it without having to hold down BREAK the whole time. (One obvious solution is to wire my board to the 6502's /RESET line, but I'm hoping for something that works without any extra hardware.)
You've now got me curious to know precisely what happens during reset. The datasheet says of ~RST "during the time that this line is held low, writing to or from the microprocessor is inhibited" without giving any clue what on earth that means for a bus that can't idle. It might be time to bring out the logic analyser.
I think you'll see the address bus holding the value that was present prior to the reset, and the data bus tristated. This may or may not result in the data bus being driven though... for example if RnW=1 and A=&0000, the RAM will end up driving the data bus during the high clock period. Given my results last night, I think it's safe to say that the 6502 doesn't drive the data bus during reset if it wasn't doing so before reset. If you can get a CPLD to put the system into reset when RnW=1, I wonder if it would drive the bus while in reset or not.

One thing I'd like to see is what the address bus does once you execute an 0x02 ("KIL") instruction. Does it stay constant at the address of the instruction, or address+1? Or does it jump somewhere else? Visual6502 shows it jumping to &fffe then &ffff, but I don't think that can be happening on my machine, because that would result in OS ROM reads interfering with my board's bus usage.
I fear your plight may be even worse if you plug into one of the other ROM sockets on a Master (or in a cartridge), by the way: so far as I can see, that doesn't even have a buffer isolating the memory subsystem from the CPU bus during the Video ULA's half of each 2MHz cycle!
Good thing I can just plug into the MOS ROM socket! That's much more interesting than the other sockets anyway, because I get to provide 7 ROMs rather than just one or two :)
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by crj » Fri Mar 16, 2018 8:13 am

myelin wrote:(One obvious solution is to wire my board to the 6502's /RESET line, but I'm hoping for something that works without any extra hardware.)
Another - though it may be a bit late now - would be to have a buffer between your circuitry and the bus.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Fri Mar 16, 2018 8:18 am

crj wrote:Another - though it may be a bit late now - would be to have a buffer between your circuitry and the bus.
I wish! Barely enough space / pin count in my xc9572xl to make the existing board work, let alone buffering the D bus. Time to move up to the 95144 perhaps!
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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by crj » Fri Mar 16, 2018 8:21 am

Er... I was thinking in terms of a separate component. Hence the "too late" remark, given you've already spun the board. /-8

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by SteveBagley » Fri Mar 16, 2018 11:53 am

myelin wrote:Exactly. So I need a way to get the CPU to issue continuous reads from memory-mapped I/O locations or paged ROMs that aren't present :) The latter is easier, because my board acts as a paged ROM.
How about loading a branch instruction into the VIAs registers and jumping to it?

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by tricky » Fri Mar 16, 2018 1:53 pm

myelin wrote:...Visual6502 shows it jumping to &fffe then &ffff...
I don't know about the Kil instrucrtion (never heard of it before!), but some of the "undocumented" instructions don't do on the Visual6502 what they do on a real one. They did "fix" this for all the reliable ones by simulating the gates in an "analogue" way on FPGA as some lines are contested. That is they are pulled in different directions and in the JS version, the "last" one wins, but in the "analogue" version, the majority wins.
Unless I have dreamt the whole thing.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by crj » Fri Mar 16, 2018 6:24 pm

SteveBagley wrote:How about loading a branch instruction into the VIAs registers and jumping to it?
Sneaky! But you'd need two consecutive registers you could control the content of, wouldn't you? Though IRB works as expected when DDRB=1, the Advanced User Guide p402 documents IRA with DDRA=1 as behaving rather differently (to detect drive clash on a bus?).

As a further complication, you're really not expected to be running code from a memory-mapped peripheral like that, and you'd have to work out what other, potentially read-sensitive, locations the CPU would idly touch while executing a branch.

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Re: Myelin's in-system updateable MegaROM for the BBC Master 128

Post by myelin » Fri Mar 16, 2018 6:41 pm

SteveBagley wrote:How about loading a branch instruction into the VIAs registers and jumping to it?
Excellent idea, although I don't believe this would tristate the data bus... it would keep the processor away from any actual memory, but would still result in a read on every clock cycle.

crj's suggestion to add in a buffer between the data bus and the flash and CPLD makes the most sense. There's plenty of room on the PCB (all the data pins are in the bottom right hand corner, around the 'updatable master megarom' text, so I could throw a buffer chip in there and completely isolate everything. For the next version, I guess! I'm tempted to do a four-socket RAM/ROM board that provides independent access over USB to all 256kB... although I already have far too many projects to work on, so maybe not ;)

I think I'm going to experiment a bit more with trying to time things so the flash access happens during the low part of the clock cycle, when the data bus is presumably undriven... I think I can probably *just* pull that off with an 8MHz SPI clock.
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