Open Source Logic Analyzer Experiments

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dominicbeesley
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Re: Open Source Logic Analyzer Experiments

Post by dominicbeesley » Fri Dec 01, 2017 2:04 pm

Thanks all,

I'd got the, possibly mistaken, impression that the tube signal was being hijacked rather than just read. I will crimp on an extra end!

D

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Fri Dec 01, 2017 2:55 pm

A 3-connector Tube Cable (aka an old IDE cable) is a great way of connecting a logic analyzer to snoop on the Tube protocol.

Here's a photo of the FX2 board hooked up with jumper wires (GND, D7..D0, RnW, Phi2):
IMG_1141.JPG
On a reasonably fast Linux machine, you can actually run the capture and decoding continuously:

Code: Select all

fx2pipe -d=1d50:608d  -a 2>/dev/null | ./decode6502  -s -h -y --sync= --phi2= | egrep "FEE1|FEE3|FEE5|FEE7"
Running like this on my 10 year old dev machine (Core2 Quad Q9550 @ 2.83GHz) the decoder uses 75% of one core. So it's just keeping up!

And on pressing break you get something like this:

Code: Select all

B630 : AD E1 FE : LDA FEE1       : 4 : A=0A X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=1
B630 : AD E1 FE : LDA FEE1       : 4 : A=41 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=63 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=6F X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=72 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=6E X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=20 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=54 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=55 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=42 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=45 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=20 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=36 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=35 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=30 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=32 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=20 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=36 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=34 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=4B X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=0A X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=0A X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=0D X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=0 C=0
B630 : AD E1 FE : LDA FEE1       : 4 : A=00 X=FF Y=1F SP=9B N=0 V=1 D=0 I=1 Z=1 C=0
06A3 : 8D E7 FE : STA FEE7       : 4 : A=05 X=00 Y=0E SP=9D N=0 V=1 D=0 I=1 Z=0 C=0
06A3 : 8D E7 FE : STA FEE7       : 4 : A=80 X=00 Y=0E SP=9D N=0 V=1 D=0 I=1 Z=1 C=0
069A : 8D E3 FE : STA FEE3       : 4 : A=80 X=00 Y=0E SP=A0 N=0 V=1 D=0 I=0 Z=1 C=0
003B : AD E1 FE : LDA FEE1       : 4 : A=3E X=FF Y=0E SP=FF N=0 V=1 D=0 I=0 Z=0 C=0
004B : AE E3 FE : LDX FEE3       : 4 : A=3E X=0A Y=0E SP=FF N=0 V=1 D=0 I=0 Z=0 C=0
06CA : AD E3 FE : LDA FEE3       : 4 : A=FF X=04 Y=0E SP=FD N=1 V=1 D=0 I=0 Z=0 C=0
06CA : AD E3 FE : LDA FEE3       : 4 : A=20 X=03 Y=0E SP=FD N=0 V=1 D=0 I=0 Z=0 C=0
06CA : AD E3 FE : LDA FEE3       : 4 : A=EE X=02 Y=0E SP=FD N=1 V=1 D=0 I=0 Z=0 C=0
06CA : AD E3 FE : LDA FEE3       : 4 : A=07 X=01 Y=0E SP=FD N=0 V=1 D=0 I=0 Z=0 C=0
06CA : AD E3 FE : LDA FEE3       : 4 : A=00 X=00 Y=0E SP=FD N=0 V=1 D=0 I=0 Z=1 C=0
Crude, but quite effective.

Dave

crj
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Re: Open Source Logic Analyzer Experiments

Post by crj » Fri Dec 01, 2017 5:14 pm

cmorley wrote:IIRC the 80 conductor Ultra ATA cables are wired differently so ignore them.
Original ATA interleaved signal with ground so supported 20 signals. Ultra ATA does a trick where the connector grounds alternate ways on the 80-conductor cable so almost all the 40 pins of the connector can be used for signals.

Annoyingly, although it's fairly easy to find the Ultra ATA pinout, it's much harder to discover which of the ground pins the interleaved conductors are tied to. It might be fine for Tube; it might not.

This is somewhat academic, however, since all Ultra ATA connectors have pin 20 keyed...

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Re: Open Source Logic Analyzer Experiments

Post by cmorley » Fri Dec 01, 2017 5:59 pm

crj wrote: Original ATA interleaved signal with ground so supported 20 signals. Ultra ATA does a trick where the connector grounds alternate ways on the 80-conductor cable so almost all the 40 pins of the connector can be used for signals.

Annoyingly, although it's fairly easy to find the Ultra ATA pinout, it's much harder to discover which of the ground pins the interleaved conductors are tied to. It might be fine for Tube; it might not.

This is somewhat academic, however, since all Ultra ATA connectors have pin 20 keyed...
Not true, there are only 7 ground lines on the IDE pinout. All the grounds are connected on an Ultra ATA cable so you'd short out 6 signals which are on the even pins on the Tube. Hence useless for Tube & Pi, FPGA etc

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Re: Open Source Logic Analyzer Experiments

Post by crj » Fri Dec 01, 2017 6:23 pm

cmorley wrote: Not true, there are only 7 ground lines on the IDE pinout.
Sorry, yes. Floppy/hard drive brainfart.
All the grounds are connected on an Ultra ATA cable
Well, that's at least as large a showstopper as the plugged pin, then, though the plugged pin was already fatal.

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1024MAK
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Re: Open Source Logic Analyzer Experiments

Post by 1024MAK » Fri Dec 01, 2017 7:11 pm

Yes, Ultra ATA cables are only useful for Ultra ATA drives :(

Whereas the older, 40 way IDE (ATA) cables that had/have standard IDC (line) socket(s) (with no "pins" plugged) can easily be repurposed :D

However, some 40 way IDE (ATA) cables do have "pin" 20 blocked, these are less useful :(

Mark

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myelin
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Re: Open Source Logic Analyzer Experiments

Post by myelin » Thu Dec 07, 2017 9:00 am

I just sent off the PCB order for the fx2_tube_cartridge_adapter to Seeed. Fingers crossed!

I ended up managing to implement everything I was hoping for --

- FX2 wiring for BBC via Tube port, Electron via cartridge interface (with clock fixup), Master via cartridge interface
- PiTubeDirect level shifting for BBC/Master via Tube port, Electron via cartridge interface
- Tube interface for the Electron

I have the FX2 on the front of the cartridge and the Pi on the back, so it should be possible to debug the machine while PiTubeDirect is active.

I'll post back once the boards arrive and I get to try them out. Maybe I'll finally be able to tell what's going wrong with my broken Plus 1!
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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marcusjambler
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Re: Open Source Logic Analyzer Experiments

Post by marcusjambler » Thu Dec 07, 2017 9:56 am

=D> =D>

Registering interest for a built or bare board :D

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myelin
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Re: Open Source Logic Analyzer Experiments

Post by myelin » Fri Dec 15, 2017 11:58 pm

Boards are here! May have time to get one built and tested next week, otherwise sometime after Xmas :)
2017-12 fx2tube sm.jpeg
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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myelin
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Re: Open Source Logic Analyzer Experiments

Post by myelin » Wed Dec 20, 2017 7:23 am

Testing time!

The board powered up and my franken-Elk with the FPGA and PiTubeDirect hooked into the CPU socket booted just fine with it connected via the Minus One. I copied the elk_pi_tube_direct VHDL and updated it to run on the new board, and it built and programmed okay.

fx2pipe wouldn't capture anything for a while:

- It wouldn't build on my Mac, so I switched to a Linux box.
- The fx2 board enumerated as a Saleae Logic (!), so I changed the USB ID passed to fx2pipe.
- fx2pipe would fail to start if I didn't run it as root.
- I forgot to fit the adapter board's RnW and clock jumpers, so the synchronous capture mode was just hanging.

Finally it performed a capture with this:

Code: Select all

sudo fx2pipe -d=0925:3881 -a -n=5M > data.bin
./decode6502 -s -h -y --phi2= data.bin > data.txt
Once I got all that sorted, it captured just fine, but decode6502 just showed that the bus was alternating between 01 and 00, and data.txt looked like 2.5M lines of this:

Code: Select all

???? : 01 00    : ORA (00,X)     : 1 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=?
I realized that my VHDL was designed for the PiTubeDirect adapter, and was only driving the level-shifted bus when requests to &FCEx were being made (i.e. Tube accesses). Changing it so that it would *always* copy the CPU data bus over to the 3.3V bus resulted in an endless repetition of this:

Code: Select all

FFFE : 20 00 00 : JSR 0000       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=0
0000 : CE 00 00 : DEC 0000       : 1 : A=00 X=00 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=0
0003 : E0 00    : CPX #00        : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0005 : E2       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0006 : E7       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0007 : E1 00    : SBC (00,X)     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0009 : B8       : CLV            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
000A : 6C 00 00 : JMP (0000)     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0000 : 6C 00 00 : JMP (0000)     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0000 : 2C 00 00 : BIT 0000       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0003 : 02       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0004 : D2       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0005 : E1 00    : SBC (00,X)     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0007 : 08       : PHP            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=0 prediction failed
0008 : 78       : SEI            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=0
0009 : 33       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=0
000A : 78       : SEI            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=0
000B : BD 00 00 : LDA 0000,X     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=0
000E : BD 00 00 : LDA 0000,X     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=0
0011 : CC 00 00 : CPY 0000       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0014 : 02       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0015 : E0 00    : CPX #00        : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0017 : DD 00 00 : CMP 0000,X     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
001A : D5 00    : CMP 00,X       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
001C : 02       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
001D : E0 00    : CPX #00        : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
001F : F0 00    : BEQ 0021       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0021 : 72       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0022 : A8       : TAY            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0023 : FB       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
0024 : 28       : PLP            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=0
0025 : 38       : SEC            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0026 : 50 00    : BVC 0028       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0028 : 33       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0029 : 38       : SEC            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
002A : 60       : RTS            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0001 : 60       : RTS            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0001 : 48       : PHA            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0002 : 33       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0003 : E7       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0004 : E2       : ???            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0005 : E1 00    : SBC (00,X)     : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
0007 : B0 00    : BCS 0009       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
0009 : 66 00    : ROR 00         : 1 : A=00 X=00 Y=00 SP=?? N=1 V=0 D=0 I=0 Z=0 C=0
000B : E0 00    : CPX #00        : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
000D : 60       : RTS            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
0001 : B0 00    : BCS 0003       : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
0003 : 46 00    : LSR 00         : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=0
0005 : 60       : RTS            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=0
0001 : 48       : PHA            : 1 : A=00 X=00 Y=00 SP=?? N=0 V=0 D=0 I=0 Z=1 C=0
pc: prediction failed at FFFE old pc was 0002
This is getting somewhere, because the system is just sitting at the cursor, so I'd expect to see the same thing repeated forever. Time to implement the clock cleanup!
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Dec 20, 2017 8:01 am

myelin wrote:

Code: Select all

sudo fx2pipe -d=0925:3881 -a -n=5M > data.bin
./decode6502 -s -h -y --phi2= data.bin > data.txt
Two suggestions:

1. Make sure you are building fx2pipe from the source in my repository, as the last commit is important
https://github.com/hoglet67/6502Decoder ... er/fx2pipe

2. Add the following option to decode6502, to switch to the sync-less decoder:

Code: Select all

--sync=
(as you don't have sync connected on the cartridge port)

Dave

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myelin
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Re: Open Source Logic Analyzer Experiments

Post by myelin » Wed Dec 20, 2017 8:17 am

Should have written this post quicker -- figured that out a few mins ago but hadn't got my report out yet! Changing the command line to this fixed everything:

Code: Select all

./decode6502 -s -h -y --phi2= --sync= --rst= data.bin > data.txt
Now I get an endless repetition of this, which seems much saner!

Code: Select all

DC75 : AE 41 02 : LDX 0241       : 4 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
DC78 : 20 2E E3 : JSR E32E       : 6 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E32E : 2C 5F 02 : BIT 025F       : 4 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E331 : 30 60    : BMI E393       : 2 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E333 : 8A       : TXA            : 2 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E334 : 2D 45 02 : AND 0245       : 4 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E337 : D0 AC    : BNE E2E5       : 2 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E339 : AD 5D 02 : LDA 025D       : 4 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E33C : D0 27    : BNE E365       : 2 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E33E : AD 68 02 : LDA 0268       : 4 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E341 : F0 A2    : BEQ E2E5       : 4 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E2E5 : 20 CE E1 : JSR E1CE       : 6 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E1CE : B8       : CLV            : 2 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E1CF : 6C 2C 02 : JMP (022C)     : 5 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E1D2 : 08       : PHP            : 3 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E1D3 : 78       : SEI            : 2 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
E1D4 : BD CC 02 : LDA 02CC,X     : 4 : A=E0 X=00 Y=DD SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
E1D7 : DD D5 02 : CMP 02D5,X     : 4 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
E1DA : F0 72    : BEQ E24E       : 4 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
E24E : 28       : PLP            : 4 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E24F : 38       : SEC            : 2 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E250 : 60       : RTS            : 6 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E2E8 : B0 66    : BCS E350       : 4 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E350 : B0 46    : BCS E398       : 3 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E398 : 48       : PHA            : 3 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E399 : 20 50 E9 : JSR E950       : 6 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E950 : AD 22 08 : LDA 0822       : 4 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E953 : F0 20    : BEQ E975       : 3 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E975 : 60       : RTS            : 6 : A=00 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
E39C : 68       : PLA            : 4 : A=E0 X=00 Y=DD SP=?? N=1 V=0 D=0 I=0 Z=0 C=1
E39D : 38       : SEC            : 2 : A=E0 X=00 Y=DD SP=?? N=1 V=0 D=0 I=0 Z=0 C=1
E39E : 60       : RTS            : 6 : A=E0 X=00 Y=DD SP=?? N=1 V=0 D=0 I=0 Z=0 C=1
DC7B : 90 11    : BCC DC8E       : 2 : A=E0 X=00 Y=DD SP=?? N=1 V=0 D=0 I=0 Z=0 C=1
DC7D : 24 E6    : BIT E6         : 3 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
DC7F : 50 F0    : BVC DC71       : 3 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
DC71 : 24 FF    : BIT FF         : 3 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
DC73 : 30 16    : BMI DC8B       : 2 : A=E0 X=00 Y=DD SP=?? N=0 V=0 D=0 I=0 Z=1 C=1
Here it is capturing the Electron's reset sequence:

Code: Select all

???? :          : RESET !!       : 9 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
D8D2 : A9 40    : LDA #40        : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D8D4 : 8D 00 0D : STA 0D00       : 4 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D8D7 : 78       : SEI            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D8D8 : D8       : CLD            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
D8D9 : A2 FF    : LDX #FF        : 2 : A=40 X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
D8DB : 9A       : TXS            : 2 : A=40 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8DC : E8       : INX            : 2 : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8DD : 8E 00 FE : STX FE00       : 4 : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8E0 : 8E 8D 02 : STX 028D       : 4 : A=40 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8E3 : A9 F8    : LDA #F8        : 2 : A=F8 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8E5 : 8D 05 FE : STA FE05       : 4 : A=F8 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8E8 : AD 00 FE : LDA FE00       : 4 : A=90 X=00 Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D8EB : 29 02    : AND #02        : 2 : A=00 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=?
D8ED : 49 02    : EOR #02        : 2 : A=02 X=00 Y=?? SP=FF N=0 V=? D=0 I=1 Z=0 C=?
D8EF : 48       : PHA            : 3 : A=02 X=00 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=?
D8F0 : F0 09    : BEQ D8FB       : 2 : A=02 X=00 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=?
D8F2 : AD 58 02 : LDA 0258       : 4 : A=00 X=00 Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=?
D8F5 : 4A       : LSR A          : 2 : A=00 X=00 Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=0
D8F6 : C9 01    : CMP #01        : 2 : A=00 X=00 Y=?? SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D8F8 : D0 18    : BNE D912       : 4 : A=00 X=00 Y=?? SP=FE N=1 V=? D=0 I=1 Z=0 C=0
D912 : A2 3A    : LDX #3A        : 2 : A=00 X=3A Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=0
D914 : 20 1E EC : JSR EC1E       : 6 : A=00 X=3A Y=?? SP=FC N=0 V=? D=0 I=1 Z=0 C=0
EC1E : F0 28    : BEQ EC48       : 2 : A=00 X=3A Y=?? SP=FC N=0 V=? D=0 I=1 Z=0 C=0
EC20 : 48       : PHA            : 3 : A=00 X=3A Y=?? SP=FB N=0 V=? D=0 I=1 Z=0 C=0
EC21 : 8A       : TXA            : 2 : A=3A X=3A Y=?? SP=FB N=0 V=? D=0 I=1 Z=0 C=0
EC22 : 29 3F    : AND #3F        : 2 : A=3A X=3A Y=?? SP=FB N=0 V=? D=0 I=1 Z=0 C=0
EC24 : 48       : PHA            : 3 : A=3A X=3A Y=?? SP=FA N=0 V=? D=0 I=1 Z=0 C=0
EC25 : 20 F8 EC : JSR ECF8       : 6 : A=3A X=3A Y=?? SP=F8 N=0 V=? D=0 I=1 Z=0 C=0
ECF8 : 08       : PHP            : 3 : A=3A X=3A Y=?? SP=F7 N=0 V=0 D=0 I=1 Z=0 C=0
ECF9 : 48       : PHA            : 3 : A=3A X=3A Y=?? SP=F6 N=0 V=0 D=0 I=1 Z=0 C=0
ECFA : 29 3F    : AND #3F        : 2 : A=3A X=3A Y=?? SP=F6 N=0 V=0 D=0 I=1 Z=0 C=0
ECFC : 4A       : LSR A          : 2 : A=1D X=3A Y=?? SP=F6 N=0 V=0 D=0 I=1 Z=0 C=0
ECFD : 4A       : LSR A          : 2 : A=0E X=3A Y=?? SP=F6 N=0 V=0 D=0 I=1 Z=0 C=1
ECFE : AA       : TAX            : 2 : A=0E X=0E Y=?? SP=F6 N=0 V=0 D=0 I=1 Z=0 C=1
ECFF : BD 17 ED : LDA ED17,X     : 4 : A=9F X=0E Y=?? SP=F6 N=1 V=0 D=0 I=1 Z=0 C=1
ED02 : 85 FB    : STA FB         : 3 : A=9F X=0E Y=?? SP=F6 N=1 V=0 D=0 I=1 Z=0 C=1
ED04 : 8D C2 02 : STA 02C2       : 4 : A=9F X=0E Y=?? SP=F6 N=1 V=0 D=0 I=1 Z=0 C=1
ED07 : BD 25 ED : LDA ED25,X     : 4 : A=FF X=0E Y=?? SP=F6 N=1 V=0 D=0 I=1 Z=0 C=1
ED0A : 85 FA    : STA FA         : 3 : A=FF X=0E Y=?? SP=F6 N=1 V=0 D=0 I=1 Z=0 C=1
ED0C : 8D C1 02 : STA 02C1       : 4 : A=FF X=0E Y=?? SP=F6 N=1 V=0 D=0 I=1 Z=0 C=1
ED0F : 68       : PLA            : 4 : A=3A X=0E Y=?? SP=F7 N=0 V=0 D=0 I=1 Z=0 C=1
ED10 : 29 03    : AND #03        : 2 : A=02 X=0E Y=?? SP=F7 N=0 V=0 D=0 I=1 Z=0 C=1
ED12 : AA       : TAX            : 2 : A=02 X=02 Y=?? SP=F7 N=0 V=0 D=0 I=1 Z=0 C=1
ED13 : BD 86 F0 : LDA F086,X     : 4 : A=04 X=02 Y=?? SP=F7 N=0 V=0 D=0 I=1 Z=0 C=1
ED16 : 28       : PLP            : 4 : A=04 X=02 Y=?? SP=F8 N=0 V=0 D=0 I=1 Z=0 C=0
ED17 : 60       : RTS            : 6 : A=04 X=02 Y=?? SP=FA N=0 V=0 D=0 I=1 Z=0 C=0
EC28 : 85 FC    : STA FC         : 3 : A=04 X=02 Y=?? SP=FA N=0 V=0 D=0 I=1 Z=0 C=0
I think we can say that my board is working, at least for monitoring the Electron's bus in my particular case. I've posted a couple of boards off to Hoglet today, and am happy to do the same for anybody prepared to acquire the necessary parts and solder up their own board, at least while I still have supplies (currently: 7 boards available). Post in here and send me a PM, and I'll send some boards out when I get a minute :)
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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Re: Open Source Logic Analyzer Experiments

Post by myelin » Wed Dec 20, 2017 9:44 am

Time to go to bed, but I ended up trying it out with PiTubeDirect after all, after verifying the bus timing with BigEd. It works! I have it running the 'ball of yarn' test program that comes with the 65C02 copro right now, and the FX2 is capturing nicely at the same time. So I think this board is a success :)
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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Re: Open Source Logic Analyzer Experiments

Post by myelin » Thu Jan 04, 2018 7:56 pm

FYI I've started a new thread for discussion of my adapter board: http://www.stardot.org.uk/forums/viewto ... =3&t=14319
SW/EE from New Zealand, now in Mountain View, CA, making BBC/Electron hardware projects for fun.
Most popular: fast serial port, FX2+PiTubeDirect Tube/Cartridge adapter, USB cart interface.

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tricky
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Re: Open Source Logic Analyzer Experiments

Post by tricky » Mon Feb 05, 2018 9:39 pm

I have one of these £3.31, no cables that I ordered a while back, can't even remember what for now.
It looks like it is a Geeetech, the sigrock software has decided that it is compatible with fx2lafw, but that is about as far as I have got!
I don't think Windows7 64bit is its primary target, I also don't know if it is programmed as a logic analyser, if it needs to be reprogrammed, somethings else I know nothing about!

Off to read this thread again as most of it has dropped off my memory FIFO!

EDIT:
Looks like sigrok is happy with WinUSB or libusbK, but not the other two drivers.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Mon Feb 05, 2018 10:05 pm

That board should work - are you thinking of hooking it up the the Tube initially?

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Re: Open Source Logic Analyzer Experiments

Post by tricky » Mon Feb 05, 2018 10:21 pm

Seems like a plan, I do occasionally need to find out what went wrong on hardware that isn't reproducible on an emulator and this seems like one way of debugging really nasty timing issues.
I also have a few beebs that need looking at, which will also be easier with this.

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Re: Open Source Logic Analyzer Experiments

Post by fordp » Tue Feb 06, 2018 8:23 am

tricky wrote:Seems like a plan, I do occasionally need to find out what went wrong on hardware that isn't reproducible on an emulator and this seems like one way of debugging really nasty timing issues.
I also have a few beebs that need looking at, which will also be easier with this.
This set-up with your ROM should be great. I have ordered the correct CPLDs now :D

Maybe a thread/ Github for your ROM is called for?
FordP (Simon Ellwood)
Time is an illusion. Lunchtime, doubly so!

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tricky
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Re: Open Source Logic Analyzer Experiments

Post by tricky » Tue Feb 06, 2018 9:51 am

quote="fordp"]...

This set-up with your ROM should be great. I have ordered the correct CPLDs now :D

Maybe a thread/ Github for your ROM is called for?[/quote]

My ROM?
It only reads from itself and writes only to ram, so it might not be as useful as you think.
It could have some reads added to give a trace something to check.

I have not had any success with git(hub), I really only use perforce, but anyone is welcome to take my source and do whatever they want, short of charging for it.

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Re: Open Source Logic Analyzer Experiments

Post by marcusjambler » Tue Feb 06, 2018 1:24 pm

Hi All

My FX2LP board arrived :) But I cant find drivers for it for Win 10...
Is this project a Linux only deal??
A bit of hand holding from someone would help me a lot [-o<

Marcus

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Feb 06, 2018 4:33 pm

marcusjambler wrote: My FX2LP board arrived :) But I cant find drivers for it for Win 10...
Is this project a Linux only deal??
A bit of hand holding from someone would help me a lot [-o<
It's not intentionally Linux only, but I don't use Windows much myself, and I don't have any Windows 10 machines to play with.

Also, the C code I've written should be portable, but again I've only ever built it on Linux.

Sigrok runs under Windows 10, and they claim to support this hardware, so it must be possible.

There are some Windows specific instructions for this board on the Hobby Components forum:
http://forum.hobbycomponents.com/viewto ... 102&t=1891

Is that where you bought from?

(The reason I as is some of the "cheap" boards on eBay seem to have a different USB ID, which can cause complications.)

Anyway, let me have a try on Windows 7 and see how far I get. Then I'll be in a better position to help.

Dave

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Re: Open Source Logic Analyzer Experiments

Post by marcusjambler » Tue Feb 06, 2018 5:21 pm

Hobby Components
Yes its one of their £12ish kits

Thanks for the link and help in advance Dave :D

Marcus

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Re: Open Source Logic Analyzer Experiments

Post by tricky » Tue Feb 06, 2018 5:55 pm

I had troubles with drivers on win7, but using the sigrok "Zadig" utility, I was able to swap the drivers until I found one that made the sigrok SW see the board (I think I had to tick the top option in one of the Zadig menus to list all USB devices before I could select my cheapo board.

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Re: Open Source Logic Analyzer Experiments

Post by marcusjambler » Tue Feb 06, 2018 6:25 pm

The win sigrok download link on the Hobby components page is currently down :(

http://sigrok.org/jenkins/job/sigrok-cr ... taller.exe

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Re: Open Source Logic Analyzer Experiments

Post by Coeus » Tue Feb 06, 2018 6:35 pm

hoglet wrote:(The reason I as is some of the "cheap" boards on eBay seem to have a different USB ID, which can cause complications.)
You remind me of when I connected an FTDI USB/Serial converter to my QNAP NAS to capture the output of an energy monitor and it was detected as a UPS. Seems the lazy UPS manufacturer had adapter a serial UPS to USB with the FTDI converter but left the USB ID of the FTDI module at the default rather than doing the right thing of setting it to something suitable for the complete product it was now part of.

Back onto the logic analyser I was looking at the FTDI option as that seemed like the cheaper option but I am beginning to think there is not much in it, particularly once you have worked out some way of connecting.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Feb 06, 2018 6:53 pm

marcusjambler wrote:The win sigrok download link on the Hobby components page is currently down :(

http://sigrok.org/jenkins/job/sigrok-cr ... taller.exe
I've done my best to put together some Windows instructions here:
viewtopic.php?p=182769#p182769

Dave

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Re: Open Source Logic Analyzer Experiments

Post by marcusjambler » Tue Feb 06, 2018 10:38 pm

Thanks :)

Fingers crossed, I have the Pulseview software looking at my FX2LP through the Zadig driver.
Pulseview is currently able to collect continuous flat-lining. :lol:

Next job is to make up a cable to the tube and setup the connections.

Am I correct in thinking there's no level shifting required? [-o<

Marcus

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Feb 07, 2018 7:43 am

marcusjambler wrote: Am I correct in thinking there's no level shifting required? [-o<
Correct, as long as the FX2 is powered up first and powered off last. (i.e. don't leave it attached to the Beeb with it NOT being powered via USB).
Last edited by hoglet on Wed Feb 07, 2018 9:04 am, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by tricky » Wed Feb 07, 2018 8:20 am

I think I get you, when not powered by USB?

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Feb 07, 2018 9:04 am

tricky wrote:I think I get you, when not powered by USB?
Yes, indeed, post now corrected! :oops:

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