Open Source Logic Analyzer Experiments

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Thu Aug 16, 2018 10:09 am

Elminster wrote:
Wed Aug 15, 2018 5:36 pm
Hmm. By power up break you mean from a switch on? That is what I did. I Set up fx2pipe to captue first and then powered on.I dont think I could have sent the wrong trace as the only non powerup breaks I have traced were live ones and not saved those to a file as piped stright into decode. Or I have misunderstood what you meant.
Here's the start of my reference trace:

Code: Select all

???? : RESET !!       : 7 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
D9CD : LDA #40        : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9CF : STA 0D00       : 4 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D2 : SEI            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D3 : CLD            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
D9D4 : LDX #FF        : 2 : A=40 X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
D9D6 : TXS            : 2 : A=40 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9D7 : LDA FE4E       : 4 : A=80 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9DA : ASL A          : 2 : A=00 X=FF Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=1
D9DB : PHA            : 3 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9DC : BEQ D9E7       : 3 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9E7 : LDX #04        : 2 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
LDA FE4E reads the system VIA interrupt flags - &80 means no interrupts enabled, so this is a power up reset.

Here's your trace:

Code: Select all

???? : RESET !!       : 7 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
D9CD : LDA #40        : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9CF : STA 0D00       : 4 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D2 : SEI            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D3 : CLD            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
D9D4 : LDX #FF        : 2 : A=40 X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
D9D6 : TXS            : 2 : A=40 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9D7 : LDA FE4E       : 4 : A=88 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9DA : ASL A          : 2 : A=10 X=FF Y=?? SP=FF N=0 V=? D=0 I=1 Z=0 C=1
D9DB : PHA            : 3 : A=10 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9DC : BEQ D9E7       : 2 : A=10 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9DE : LDA 0258       : 4 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
This time it returns &88, so this was not a power up reset.

You can force a power up reset on the next break by doing *FX 151,78,127 which clears all the bits in this register.

Dave
Last edited by hoglet on Thu Aug 16, 2018 10:09 am, edited 1 time in total.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 12:06 pm

Very strange, As I say the trace was from power up, so as the machine is turned off I cant really type *FX 151,78,127 :)

I start fx2pipe, turn on machine, fx2pipe starts capturing and stops when it gets to 12M, I compress it and sent to you. And I increment the data<n> for each capture, so I didnt send the wrong one, and I dont think I even have any capture where the machine was already on and I hit break.

Is that a clue that it doesnt do on power up what you expect?

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 12:17 pm

Okay that is weird I did it again and it looks like your trace. But I have only ever done them from switch on, I have never started a trace and then hit break. And not sure how I could do it accidently.

I still have the history of the last one I sent on screen, and it never got mixed up, I can see the capture and the compress.
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Last edited by Elminster on Thu Aug 16, 2018 12:19 pm, edited 2 times in total.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 12:24 pm

In fact how is that even possible. If the machine was already on the capture would not start from a RESET but would capture from where ever the machine was in the running process surely? This is the syntax I use:

Code: Select all

fx2pipe -d=0925:3881 -a -n=12M >
I just tried a capture with the machine already on and as I thought it [the capture] start straight away and doesnt wait for a reset.

Code: Select all

???? : 38       : SEC            : 2 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
???? : 60       : RTS            : 6 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
E53C : B0 55    : BCS E593       : 3 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
E593 : 60       : RTS            : 6 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
DEF0 : 90 11    : BCC DF03       : 2 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
DEF2 : 24 E6    : BIT E6         : 3 : A=?? X=?? Y=?? SP=?? N=0 V=0 D=? I=? Z=? C=1
DEF4 : 50 F0    : BVC DEE6       : 3 : A=?? X=?? Y=?? SP=?? N=0 V=0 D=? I=? Z=? C=1
DEE6 : 24 FF    : BIT FF         : 3 : A=?? X=?? Y=?? SP=?? N=0 V=0 D=? I=? Z=? C=1
DEE8 : 30 16    : BMI DF00       : 2 : A=?? X=?? Y=?? SP=?? N=0 V=0 D=? I=? Z=? C=1
DEEA : AE 41 02 : LDX 0241       : 4 : A=?? X=00 Y=?? SP=?? N=0 V=0 D=? I=? Z=1 C=1
DEED : 20 77 E5 : JSR E577       : 6 : A=?? X=00 Y=?? SP=?? N=0 V=0 D=? I=? Z=1 C=1
E577 : 2C 5F 02 : BIT 025F       : 4 : A=?? X=00 Y=?? SP=?? N=0 V=0 D=? I=? Z=? C=1
E57A : 10 05    : BPL E581       : 3 : A=?? X=00 Y=?? SP=?? N=0 V=0 D=? I=? Z=? C=1
E581 : AD 68 02 : LDA 0268       : 4 : A=00 X=00 Y=?? SP=?? N=0 V=0 D=? I=? Z=1 C=1
E584 : F0 B3    : BEQ E539       : 3 : A=00 X=00 Y=?? SP=?? N=0 V=0 D=? I=? Z=1 C=1
So I am at a loss to explain capture data5

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tricky
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Re: Open Source Logic Analyzer Experiments

Post by tricky » Thu Aug 16, 2018 12:52 pm

My initial though was that your system via was a little dodgy, or the connections to it.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 12:57 pm

tricky wrote:
Thu Aug 16, 2018 12:52 pm
My initial though was that your system via was a little dodgy, or the connections to it.
That reminds me. I swapped the 6522 around while looking at issue on this board. I may switch them back and pull the non keyboard one completely.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Thu Aug 16, 2018 1:12 pm

Elminster wrote:
Thu Aug 16, 2018 12:24 pm
So I am at a loss to explain capture data5
I agree, given what you have said, it's hard to imagine how data5 could look like this.

The value read from &FE4E was &88 - it should have been either:
- &80 after a power up break
- &D2 after a normal break (T1 interrupt, CB1 interrupt, CA1 interrupt)

I wonder if this is a clue to the problem you are having?

Have you tried changing the system VIA?

It's difficult to see how this would affect the video, but maybe it's unrelated. I bad system VIA might well cause random hanging.

Dave

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 1:21 pm

Tricky triggered something by saying VIA above.

If you remember I said my beeb has got worse (as well as the video issue) in that the system ow seemed to randomly hang.

One of the things I did was swap the 6522s around to see if it made a differnece, and I never swapped them back. It is feasible there is some sort of fault on the I/O 6522, which is now in the keyboard slot, and that is causing the machine to think the keyboard is missing and halt 9and doing weird things to the logic anal trace).

I have removed both 6522s now, and fitted a brand new wdc6522n, I will now soak test and see if that solves my random halt issue. I do seem to get more response from the screen changing to different weirdness when I blind type mode X (possibly I had 3 issues if it still hangs) . So that might be my secondary issue fixed.

So I may have got something useful from doing the logical analyser trace after all.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 1:43 pm

Maybe a redherring. Still hangs eventuall with a new 6522, have put the original 6522 keyboard 6522 into the keyboard and left out the IO 6522 (which does seem to have a less responsible keyboard, although not easy o tell with no screen). But this still might have been useful if that 6522 has a fault. I shall go back to my other probing now I think.

Watching fx2pipe/decode free running to the screen it loks like, as expected the Beeb is just loops around the IRQ handling code here forever ( well until it eventually freezes, might check chip temp to see if something is overheating, although the cover is off so must be a lot of heat)

http://mdfs.net/Docs/Comp/BBC/OS1-20/DC1C

Code: Select all

DC1C : 85 FC    : STA FC         : 3 : A=CF X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1 prediction failed
DC1E : 68       : PLA            : 4 : A=B5 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
DC1F : 48       : PHA            : 3 : A=B5 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
DC20 : 29 10    : AND #10        : 2 : A=10 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC22 : D0 03    : BNE DC27       : 3 : A=10 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC27 : 8A       : TXA            : 2 : A=04 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC28 : 48       : PHA            : 3 : A=04 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC29 : BA       : TSX            : 2 : A=04 X=?? Y=00 SP=?? N=? V=0 D=0 I=1 Z=? C=1
DC2A : BD 03 01 : LDA 0103,X     : 4 : A=07 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC2D : D8       : CLD            : 2 : A=07 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC2E : 38       : SEC            : 2 : A=07 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC2F : E9 01    : SBC #01        : 2 : A=06 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC31 : 85 FD    : STA FD         : 3 : A=06 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC33 : BD 04 01 : LDA 0104,X     : 4 : A=80 X=?? Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
DC36 : E9 00    : SBC #00        : 2 : A=80 X=?? Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
DC38 : 85 FE    : STA FE         : 3 : A=80 X=?? Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
DC3A : A5 F4    : LDA F4         : 3 : A=04 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC3C : 8D 4A 02 : STA 024A       : 4 : A=04 X=?? Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC3F : 86 F0    : STX F0         : 3 : A=04 X=D4 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC41 : A2 06    : LDX #06        : 2 : A=04 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
DC43 : 20 68 F1 : JSR F168       : 6 : A=04 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F168 : A5 F4    : LDA F4         : 3 : A=04 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16A : 48       : PHA            : 3 : A=04 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16B : 8A       : TXA            : 2 : A=06 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16C : A2 0F    : LDX #0F        : 2 : A=06 X=0F Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=0F Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=0F Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=0F Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=0E Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=0E Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=0E Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=0E Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=0E Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=0D Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=0D Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=0D Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=0D Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=0D Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=0C Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=0C Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=0C Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=0C Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=0C Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=0B Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=0B Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=0B Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=0B Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=0B Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=0A Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=0A Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=0A Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=0A Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=0A Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=09 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=09 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=09 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=09 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=09 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F183 : CA       : DEX            : 2 : A=06 X=08 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=08 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=08 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=08 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=08 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=07 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=07 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=07 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=07 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=07 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F183 : CA       : DEX            : 2 : A=06 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F174 : 10 0D    : BPL F183       : 2 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F176 : 86 F4    : STX F4         : 3 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F178 : 8E 30 FE : STX FE30       : 4 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F17B : 20 03 80 : JSR 8003       : 6 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
8003 : 1F       : ???            : 7 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
8004 : 60       : RTS            : 6 : A=06 X=06 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F17E : AA       : TAX            : 2 : A=06 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F17F : F0 05    : BEQ F186       : 2 : A=06 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F181 : A6 F4    : LDX F4         : 3 : A=06 X=06 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F183 : CA       : DEX            : 2 : A=06 X=05 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=05 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=05 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=05 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F174 : 10 0D    : BPL F183       : 3 : A=06 X=05 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F183 : CA       : DEX            : 2 : A=06 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F184 : 10 E8    : BPL F16E       : 3 : A=06 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
F16E : FE A1 02 : INC 02A1,X     : 7 : A=06 X=04 Y=00 SP=?? N=0 V=0 D=0 I=1 Z=1 C=1
F171 : DE A1 02 : DEC 02A1,X     : 7 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F174 : 10 0D    : BPL F183       : 2 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F176 : 86 F4    : STX F4         : 3 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F178 : 8E 30 FE : STX FE30       : 4 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F17B : 20 03 80 : JSR 8003       : 6 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
8003 : 80       : ???            : 2 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
pc: prediction failed at 8005 old pc was 8008
8005 : 00 00    : BRK #00        : 7 : A=06 X=04 Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 1:52 pm

Yes I think I had/have 3 issues

1. Keyboard had been okay but didnt seem to be fully working any more
2. Video issue
3. Randomly halting

I have no idea when 3 started as onyl resently started probing and using logical analysing, might be new or might have been doing it when it broken 3 years ago.

I think 1. start when I switch the 6522 around and now seems to be fixed. 'Mode X' changes the screene to a differnt type of blur, but also doing '* TAPE' and 'LOAD""' I can hear the click of the relay now.

So thanks to both and Logical Analyser I think I have fixed one of my issues, shame I introduced it while trying to fix the others :)

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Re: Open Source Logic Analyzer Experiments

Post by 1024MAK » Thu Aug 16, 2018 2:23 pm

If you have a known good working Beeb, try any suspect 6522 VIAs in this...

Mark
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 2:47 pm

1024MAK wrote:
Thu Aug 16, 2018 2:23 pm
If you have a known good working Beeb, try any suspect 6522 VIAs in this...

Mark
Wouldnt help, the suspect 6522 was the one that happily worked in the Electron AP5 for several weeks (as this is the machine I borrowed it from), so if I had bet money on one not causing an issue that would have been it. I just ignoring it for now as issue resolved.

Going back to the Serial thingy above. Probably needs another thread.

*fx2,2
*fx3,1

Null modem cable between Beeb and a PC. 9600 8n1 with CTS I assume. If so doesnt seem to do much but then I have no idea if Serial even works on this machine other than the cassette relay clicks so IC7 at least partially works. (And why do they have to have a serial cable that can be plugged in the wrong way by accident)

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Thu Aug 16, 2018 2:54 pm

Any "prediction fail" from the logic analyzer decoder (once everything is in-sync and all register are know) is an indication of:
a) A bug in the decoder
b) A data sampling error (in my experience on the Beeb vary rare indeed)
c) Some kind of a hardware issue (e.g. bus contention) that's worth investigating

Do you have the lines before that?

What I often do when running live is to pipe decoder into grep, e.g.

Code: Select all

fx2pipe -d=0925:3881 -a 2>/dev/null  | ./decode6502 --phi2= -s -h -y | grep -1000 fail | tee data.log

This will capture 1000 lines before/after each fail.

Dave

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Re: Open Source Logic Analyzer Experiments

Post by BigEd » Thu Aug 16, 2018 2:58 pm

(Is it possible this Beeb's power-on-reset circuit is dodgy? Rather than the 6522.)

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 3:08 pm

This will capture 1000 lines before/after each fail.
I assumed it is just noise, it loops around that loop 1000s of time before freezing.

Code: Select all

(Is it possible this Beeb's power-on-reset circuit is dodgy? Rather than the 6522.)
The freezing issues inst related to 6502, just the keyboard not working very well issue, which is now resolved. So yes the reset circuitry could cause the freezing. I am just trying not to get distracted away from the video issue, too much.


I should probably not lok at the serial keyboard method, as another distraction. Just thought it may give some feedback that could be useful.

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Re: Open Source Logic Analyzer Experiments

Post by 1024MAK » Thu Aug 16, 2018 4:40 pm

The normal reset system uses a NE555 timer. This times whenever the system is powered up, or when the break ("reset") button is pressed.This reset signal resets the 6502 and also the user port 6522 and various other chips. This reset is available as inverted and non-inverted (/RST and RST). It's easy to test these circuits with a logic probe.

The system 6522 however is not connnected to the normal reset circuitry. Instead a seperate resistor and capacitor are used. This causes the system 6522 to be reset ONLY when the machine is switched on. It is not connected to the break key, so once the machine is on, it will not time again. The signal is shown as /RSTA on the schematic. This signal is best tested with a digital multimeter that has at least a 10M ohm input resistance, or a 'scope using a X10 probe. The voltage should be very near the +5V supply voltage within fractions of a second after power up. It is NOT a normal TTL level logic signal.

The MOS code reads some of the system 6522 registers, it is this read that causes the MOS code to either do a full power on start-up, or do a "warm" reset (Break or Control-Break).

Testing a 6522 in an Elk may not show up some faults, as usage in an Elk is somewhat different to use in the system 6522 position.

Mark
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 4:56 pm

I have already checked the 555 and it’s not gate for the rst and not rst, and seem okay. they reach places like cpu, I had planned to see what state the reset circuit was in when the machine hangs but I had to go out. But I suspect it is fine, as a non powerup reset gets it going again.

I have not checked 6522 reset was next on my list to work out how it is done, but all seems fine with the 6522s in original position. I shall perhaps play with the suspect one once I have other issues sorted. Using the action plan above.

Thanks for the suggestions.
Last edited by Elminster on Thu Aug 16, 2018 4:57 pm, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by BigEd » Thu Aug 16, 2018 5:09 pm

(I think, then, that the POR circuit is capable of freezing the machine, if it decides at some point to hold the system VIA in reset.)

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Re: Open Source Logic Analyzer Experiments

Post by 1024MAK » Thu Aug 16, 2018 5:30 pm

The NE555 reset circuitry can certainly cause "lock-ups" / "freezing". At a past ABUG, I had a machine which did this when the Beeb had been on for a while. It turned out to be a contaminated PCB in the area where the NE555 and it's timing resistor and capacitor are located. After a good clean, it no longer randomly stopped whenever it wanted and now runs as long as you like.

I have not experienced a failure of the /RSTA that feeds the system 6522, but given the value of the timing resistor (1M ohm), a fault due to contamination is certainly possible. And of course, partial component failure is always a possibility...

Mark
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 5:34 pm

Thanks. I shall keep any eye on those areas while hunting for my video issue. Should be fairly easy to spot when looking for it, if that is the case.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Thu Aug 16, 2018 9:31 pm

1024MAK wrote:
Thu Aug 16, 2018 5:30 pm

I have not experienced a failure of the /RSTA that feeds the system 6522, but given the value of the timing resistor (1M ohm), a fault due to contamination is certainly possible. And of course, partial component failure is always a possibility...

Mark
So /RSTA (pin 34 on 6522) goes low on power up only, and RST on pin 3 on 555 IC16 always flips on warm or cold rest. So that should be fairly easy to monitor while I poke about in other place. Be good if I had a 4channel scope instead of 2.

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Re: Open Source Logic Analyzer Experiments

Post by 1024MAK » Fri Aug 17, 2018 4:36 am

Elminster wrote:
Thu Aug 16, 2018 9:31 pm
So /RSTA (pin 34 on 6522) goes low on power up only, and RST on pin 3 on 555 IC16 always flips on warm or cold rest. So that should be fairly easy to monitor while I poke about in other place.
Yeah.

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Re: Open Source Logic Analyzer Experiments

Post by dominicbeesley » Sun Aug 26, 2018 11:53 am

A quick Q on this, I've got stuck

I've reinstated a cy7c board for debugging on my BBC B. And I'm getting odd behaviour when running from the command line.

These were clean installs from the sigrok site yesterday afternoon

Code: Select all

sigrok-cli -d fx2lafw -O binary  --samples 102400 --config samplerate=12M |decode6502 -s --rst= -c -y -h -d 999 |less
Is giving "almost" correct results but has patches where everything seems to go haywire for a while (it looks like corrupt values coming in from the USB) where I get a failed prediction then a long run of data where the D is F? and the clock looks slow...(see long dump at end)

It does that for a while, then seems to recover and carry on until it does it again.

If I run pulseview at 12M I get flawless results every time. So I think that this is sigrok-cli problem (or I'm doing something daft?).

The processor is a 65c02 in a BBC B on my blitter board but works ok otherwise, and as it is working fine from pulseview I discount any problems with decode6502...

Any advice greatly appreciated, I'd like to get this working from the command line so I can automate it...


long dump with debug enabled

Code: Select all

E581 : AD 68 02 : LDA 0268       : 2 : A=68 X=00 Y=?? SP=?? N=0 V=0 D=0 I=0 Z=0 C=1 prediction failed
0 f7 1 0
4167 ff 0 0 0 0
4168 ff 0 0 0 0
4169 ff 0 0 0 0
4170 f5 0 0 0 0
4171 f5 0 0 0 0
4172 f5 0 0 0 0
4173 fd 0 0 0 0
4174 fd 0 0 0 0
4175 fd 0 0 0 0
4176 f5 0 0 0 0
4177 f5 0 0 0 0
4178 f5 0 0 0 0
4179 fd 0 0 0 0
4180 fd 1 0 1 0
4181 fd 1 0 1 0
4182 f4 1 0 1 0
4183 f4 1 0 1 0
4184 f4 1 0 1 0
4185 fc 1 0 1 0
4186 fc 1 0 1 0
4187 fc 1 0 1 0
4188 f4 1 0 1 0
4189 f4 1 0 1 0
4190 f4 1 1 0 1
4191 fc 1 1 0 1
4192 fc 1 1 0 1
4193 fc 1 1 0 1
4194 f5 1 1 0 1
4195 f5 1 1 0 1
4196 f5 0 1 0 1
4197 fd 0 0 1 0
4198 fd 0 0 1 0
4199 fd 0 0 1 0
4200 f7 0 0 1 0
4201 f7 0 0 1 0
4202 f7 0 0 1 0
4203 ff 0 0 0 1
4204 ff 0 0 0 1
4205 ff 0 0 0 1
4206 f5 0 0 0 1
4207 f5 0 0 0 1
4208 f5 0 0 1 1
4209 fd 0 0 1 1
4210 fd 0 0 1 1
4211 fd 0 0 1 1
4212 f7 0 0 1 1
4213 f7 0 0 1 1
4214 f7 0 0 1 1
4215 ff 0 0 1 1
4216 ff 0 0 1 1
4217 ff 0 0 1 1
4218 f5 0 0 1 1
4219 f5 0 0 1 1
4220 f5 0 0 1 1
4221 fd 0 0 1 1
4222 fd 0 0 1 1
4223 fd 0 0 1 1
4224 f5 0 0 1 1
4225 f5 0 0 1 1
4226 f5 0 1 1 1
4227 fd 0 1 0 0
1 f5 0 0
4228 fd 0 1 0 0
4229 fd 0 1 0 0
4230 f5 0 1 0 0
4231 f5 0 1 0 0
4232 f5 0 1 0 0
4233 fd 0 1 0 0
4234 fd 0 1 0 0
4235 fd 0 1 0 0
4236 f5 0 1 0 0
4237 f5 0 1 0 0
4238 f5 0 0 0 0
4239 fd 0 0 0 0
4240 fd 0 0 1 0
4241 fd 0 0 1 0
4242 f5 0 0 1 0
4243 f5 0 0 1 0
4244 f5 0 0 0 0
4245 fd 0 0 0 0
4246 fd 0 0 1 0
4247 fd 0 0 1 0
4248 f7 0 0 1 0
4249 f7 0 0 1 0
4250 f7 0 0 1 1
4251 ff 0 0 0 1
4252 ff 0 0 0 1
4253 ff 0 0 0 1
4254 f5 0 0 0 1
4255 f5 0 0 0 1
4256 f5 0 0 0 1
4257 fd 0 0 0 1
4258 fd 0 0 0 1
4259 fd 0 0 0 1
4260 f4 0 0 0 1
4261 f4 0 0 0 1
4262 f4 1 1 0 0
4263 fc 1 1 0 0
4264 fc 1 1 0 0
4265 fc 1 1 0 0
4266 f7 1 1 0 0
4267 f7 1 1 0 0
4268 f7 0 0 0 0
4269 ff 0 0 0 1
4270 ff 0 0 0 1
4271 ff 0 0 0 1
4272 f5 0 0 0 1
4273 f5 0 0 0 1
4274 f5 0 0 0 1
4275 fd 1 0 1 1
4276 fd 1 0 1 1
4277 fd 1 0 1 1
4278 f7 1 0 1 1
4279 f7 1 0 1 1
4280 f7 1 0 1 1
4281 ff 1 0 1 1
4282 ff 1 0 1 1
4283 ff 1 0 1 1
4284 f5 1 0 1 1
4285 f5 1 0 1 1
4286 f5 1 0 1 1
4287 fd 0 0 0 1
4288 fd 0 0 0 1
4289 fd 0 0 0 1
4290 f5 0 0 0 1
4291 f5 0 0 0 1
4292 f5 0 1 0 1
4293 fd 0 1 0 0
4294 fd 0 1 0 0
4295 fd 0 1 0 0
4296 f5 0 1 0 0
4297 f5 0 1 0 0
4298 f5 0 0 0 0
4299 fd 0 0 0 0
4300 fd 0 0 0 0
4301 fd 0 0 0 0
4302 f7 0 0 0 0
4303 f7 0 0 0 0
4304 f7 0 0 0 0
4305 ff 1 0 1 1
4306 ff 1 0 1 1
4307 ff 1 0 1 1
4308 f5 1 0 1 1
4309 f5 1 0 1 1
4310 f5 1 0 1 1
4311 fd 1 0 0 0
2 fd 0 1
4312 fd 1 0 0 0
4313 fd 1 0 0 0
4314 f5 1 0 0 0
4315 f5 1 0 0 0
4316 f5 1 1 0 0
4317 fd 0 1 0 0
4318 fd 0 1 0 0
4319 fd 0 1 0 0
4320 f5 0 1 0 0
4321 f5 0 1 0 0
4322 f5 0 0 0 0
4323 fd 0 0 0 0
4324 fd 0 0 0 0
4325 fd 0 0 0 0
4326 f7 0 0 0 0
4327 f7 0 0 0 0
4328 f7 0 0 0 0
...
...
4446 f5 0 0 0 1
4447 f5 0 0 0 1
4448 f5 0 0 0 0
4449 fd 0 0 0 0
4450 fd 1 0 1 0
4451 fd 1 0 1 0
4452 f5 1 0 1 0
4453 f5 1 0 1 0
4454 f5 1 0 0 0
4455 fd 0 0 0 0
4456 fd 1 1 1 1
4457 fd 1 1 1 1
4458 f5 1 1 1 1
4459 f5 1 1 1 1
4460 f5 1 1 0 0
E584 : F7       : ???            : 3 : A=68 X=00 Y=?? SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0 f5 1 1
4461 fd 0 0 0 0
4462 fd 0 1 1 1
4463 fd 0 1 1 1
4464 f5 0 1 1 1
4465 f5 0 1 1 1
4466 f5 0 1 1 1
4467 fd 1 0 1 0
E585 : F5 68    : SBC 68,X       : 1 : A=68 X=00 Y=?? SP=?? N=0 V=0 D=0 I=0 Z=0 C=1
0 f5 1 0
4468 fd 1 0 1 0
4469 fd 1 0 1 0
4470 f7 1 0 1 0
4471 f7 1 0 1 0
4472 f7 1 0 1 0
4473 ff 0 0 0 0
4474 ff 0 0 0 0
4475 ff 0 0 0 0
4476 f5 0 0 0 0
4477 f5 0 0 0 0
4478 f5 0 0 0 0
4479 fd 1 0 0 0
4480 fd 1 0 0 0
4481 fd 1 0 0 0
4482 f7 1 0 0 0
4483 f7 1 0 0 0
4484 f7 1 0 0 0

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Sun Aug 26, 2018 12:07 pm

Is I connected direct to the cpu or via tube (e.g. Myeln’s board)? My tube connector was tarnished which caused weirdness.

Is usb or machine being saturated?

Other than that I leave to the others to make suggestions.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Sun Aug 26, 2018 1:24 pm

I would recommend breaking the command into two:

Code: Select all

sigrok-cli -d fx2lafw -O binary  --samples 102400 --config samplerate=12M > data.bin
decode6502 -s --rst= -c -y -h -d 999  data.bin | less
The reason being, the FX2 USB device doesn't have much buffering, so if there is the slightest hiccup in the system responding to it, then you can get dropped data.

If you still have an issue after doing that, then upload a binary file and I'll take a look.

Dave
Last edited by hoglet on Sun Aug 26, 2018 1:27 pm, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by dominicbeesley » Mon Aug 27, 2018 12:55 pm

Thanks both for the replies.

Elminster, It's connected to a gold plated header - I'm pretty sure the problem is not mechanical or electrical as running from PulseView gives good results.

USB and CPU are not in doubt, it's a fast machine and I've tried it direct on a motherboard dedicated usb 3 port with no other things connected. The machine is a decent i7 machine running little else. Again the fact that pulse view works I'd say would rule out load/usb or usb drivers as the issue.

Dave,

I think you've nailed it, however piping to a file had the same issues, but using the -o command line option seems to have sorted it - I suspect this may be a Cygwin specific thing...

Code: Select all


$ sigrok-cli -d fx2lafw -O binary  --samples 102400 --config samplerate=12M -o d:\\temp\\temp3.bin
$ cat /cygdrive/d/temp/temp3.bin |decode6502 -s --rst= -c -y -h -d 999 |less

The only fails I get now are reads from the ADC which appears to be genuinely playing up and putting rapidly changing garbage on the bus!

I'm back in business now and can start attacking ADFS...

Many Thanks

Dom
Last edited by dominicbeesley on Mon Aug 27, 2018 12:56 pm, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Mon Aug 27, 2018 1:11 pm

dominicbeesley wrote:
Mon Aug 27, 2018 12:55 pm
Thanks both for the replies.

Elminster, It's connected to a gold plated header - I'm pretty sure the problem is not mechanical or electrical as running from PulseView gives good results.
My point was that pulseview isn’t doing any on the fly decoding, so that working isn’t the same as piping through decode. But the machines spec doesn’t sound like an issue. I had similar spurious results with pipe through decode but is quite useful if you don’t mind the occasional oddness. Otherwise to a file works better.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Mon Aug 27, 2018 1:26 pm

Elminster wrote:
Mon Aug 27, 2018 1:11 pm
But the machines spec doesn’t sound like an issue.
Err, apart from the operating system!

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Mon Aug 27, 2018 3:05 pm

hoglet wrote:
Mon Aug 27, 2018 1:26 pm
Elminster wrote:
Mon Aug 27, 2018 1:11 pm
But the machines spec doesn’t sound like an issue.
Err, apart from the operating system!
That is a given with Windows.

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