Open Source Logic Analyzer Experiments

for bbc micro/electron hardware, peripherals & programming issues (NOT emulators!)
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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 7:23 pm

Ah yes changing the jumper on the lx2 board has fixed it, although my usb device id was different to yours

Code: Select all

ubuntu:~/6502Decoder/fx2pipe/firmware$ lsusb
Bus 001 Device 005: ID 0925:3881 Lakeview Research Saleae Logic

ubuntu:~/6502Decoder/fx2pipe/firmware$ sudo fx2pipe -d=0925:3881 -a -n=5M > data.bin
Firmware config: 0x12 0xcb 0xe0 0x0d 0x12
IO loop running...
Downloading firmware [builtin]...
Submitting max. 16 URBs to fill pipeline... 16 submitted
Right lets give it a go then.

Thanks.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 7:34 pm

As I have the 3 missing signals on the Beeb hooked up I have used

Code: Select all

./decode6502 -s -h -y --phi2=  ../data.bin > data.txt
Not tried continous yet, and as an example on boot on the Beeb I get

Code: Select all

???? :          : RESET !!       : 7 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
FDFD : BD 74 00 : LDA 0074,X     : 2 : A=74 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
FE00 : BD 34 3D : LDA 3D34,X     : 4 : A=74 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
FE03 : 7C       : ???            : 2 : A=74 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
FC00 : FC       : ???            : 2 : A=74 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
FC01 : B6 FF    : LDX FF,Y       : 2 : A=74 X=FF Y=?? SP=?? N=1 V=? D=? I=1 Z=0 C=?
FC03 : BE BD 3D : LDX 3DBD,Y     : 2 : A=74 X=BD Y=?? SP=?? N=1 V=? D=? I=1 Z=0 C=?
FC06 : BD 7E FE : LDA FE7E,X     : 4 : A=B4 X=BD Y=?? SP=?? N=1 V=? D=? I=1 Z=0 C=?
FC09 : 3E 7C FE : ROL FE7C,X     : 2 : A=B4 X=BD Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
FC0C : 7C       : ???            : 3 : A=B4 X=BD Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
34F4 : F4       : ???            : 3 : A=B4 X=BD Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
34F5 : B6 34    : LDX 34,Y       : 2 : A=B4 X=34 Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
34F7 : B6 35    : LDX 35,Y       : 3 : A=B4 X=34 Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
34F9 : B5 34    : LDA 34,X       : 3 : A=34 X=34 Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
34FB : BC B5 FE : LDY FEB5,X     : 2 : A=34 X=34 Y=B5 SP=?? N=1 V=? D=? I=1 Z=0 C=?
34FE : B5 34    : LDA 34,X       : 6 : A=34 X=34 Y=B5 SP=?? N=0 V=? D=? I=1 Z=0 C=?
3500 : F5 35    : SBC 35,X       : 3 : A=?? X=34 Y=B5 SP=?? N=? V=? D=? I=1 Z=? C=?
3502 : F4       : ???            : 2 : A=?? X=34 Y=B5 SP=?? N=? V=? D=? I=1 Z=? C=?
3503 : FC       : ???            : 2 : A=?? X=34 Y=B5 SP=?? N=? V=? D=? I=1 Z=? C=?
3504 : F4       : ???            : 3 : A=?? X=34 Y=B5 SP=?? N=? V=? D=? I=1 Z=? C=?
3505 : B5 34    : LDA 34,X       : 6 : A=34 X=34 Y=B5 SP=?? N=0 V=? D=? I=1 Z=0 C=?
....
So looks like it works on the beeb, I think you said it was untested? This is my issue 4 beeb.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 7:41 pm

It should work fine on a Model B - I've used this quite extensively.

But that trace looks very broken.

Can you zip up the data.bin and upload it and I'll take a quick look?

Dave
Last edited by hoglet on Tue Aug 14, 2018 7:42 pm, edited 2 times in total.

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Re: Open Source Logic Analyzer Experiments

Post by dp11 » Tue Aug 14, 2018 7:42 pm

Doesn't look right to me. The reset vector on a beeb points to D9CD . Executing code in the FC page is also very unlikely.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 7:47 pm

Well it is a broken Beeb, so that is quite possible. Lots of

Code: Select all

BD18 : 14       : ???            : 3 : A=14 X=14 Y=15 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1
memory modelling failed at 1690: expected 7c, actual 14
BD19 : BD 7C 16 : LDA 167C,X     : 4 : A=14 X=14 Y=15 SP=?? N=0 V=0 D=0 I=1 Z=0 C=1 prediction failed
Whatever that may mean.

Or it could just be analyzer not setup correctly of course. Let me upload some setup pictures and the dump.

Code: Select all

sudo fx2pipe -d=0925:3881  -a 2>/dev/null | ./decode6502  -s -h -y --phi2=
Eats 1.5 cores but Ubuntu is running in a VM, shame not running native on Mac.

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hoglet
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 7:50 pm

Do you have a working Model B you can capture a reset trace off first, just to check the tools are working properly.

Otherwise you might be chasing ghosts....

Oh, and don't use "live mode" for now, too many variables and if the system struggles to keep up the USB link will drop data and you'll just get junk.
Last edited by hoglet on Tue Aug 14, 2018 7:51 pm, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 7:55 pm

Pictures of setup of Analyser.

Just in case I have a cable or a jumper in the wrong place.

Plus Dump File.
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 8:05 pm

hoglet wrote:
Tue Aug 14, 2018 7:50 pm

Oh, and don't use "live mode" for now, too many variables and if the system struggles to keep up the USB link will drop data and you'll just get junk.
The VM seems to be fine and running at 35% idle, no cpu cylce wasted in wait and zero swap used. Firefox is actually using more cpu & memory on the host machine than the VM, but I never close tabs, I have about 400 open.

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Re: Open Source Logic Analyzer Experiments

Post by dp11 » Tue Aug 14, 2018 8:07 pm

realtime USB over a VM can be an issue.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 8:08 pm

hoglet wrote:
Tue Aug 14, 2018 7:50 pm
Do you have a working Model B you can capture a reset trace off first, just to check the tools are working properly.
I have a B+ sitting behind me which lives in the same storage box as the issue4. But thats my lot for testing this evening, I have planned to look through the dump this evening but if there is doubt it is not good I wont.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 8:09 pm

dp11 wrote:
Tue Aug 14, 2018 8:07 pm
realtime USB over a VM can be an issue.
Maybe. But dont have an issue with USB3 transfers to flash drives. Bit irrelevant if there is doubt even non realtime is wrong.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 8:18 pm

This is interesting....

Here's my "reference trace" for a Beeb booting:

Code: Select all

0 68 1 1 1
1 68 0 1 1
2 01 0 1 1
3 ff 0 1 1
4 01 0 1 1
5 cd 0 1 1
6 d9 0 1 1
???? :          : RESET !!
0 a9 1 1 1
1 40 0 1 1
D9CD : A9 40    : LDA #40
0 8d 1 1 1
1 00 0 1 1
2 0d 0 1 1
3 40 0 0 1
D9CF : 8D 00 0D : STA 0D00
0 78 1 1 1
1 d8 0 1 1
D9D2 : 78       : SEI
0 d8 1 1 1
1 a2 0 1 1
D9D3 : D8       : CLD
0 a2 1 1 1
1 ff 0 1 1
D9D4 : A2 FF    : LDX #FF
0 9a 1 1 1
1 ad 0 1 1
D9D6 : 9A       : TXS
Here's your trace:

Code: Select all

0 14 1 1 1
1 14 0 1 1
2 ff 0 1 1
3 14 0 1 1
4 14 0 1 1
5 dd 0 1 1
6 dd 0 1 1
???? :          : RESET !!
0 bd 1 1 1
1 54 0 1 1
DDDD : BD 54 00 : LDA 0054,X
0 9d 1 1 1
1 14 0 1 1
2 1d 0 1 1
3 54 0 0 1
DDE0 : 9D 14 1D : STA 1D14,X
0 7c 1 1 1
1 dc 0 1 1
DDE3 : 7C       : ???
0 dc 1 1 1
1 f6 0 1 1
DC00 : DC       : ???
0 b6 1 1 1
1 ff 0 1 1
DC01 : B6 FF    : LDX FF,Y
0 9e 1 1 1
1 bd 0 1 1
DC03 : 9E       : ???
(The single bits are sync, rnw, rst)

The first thing to note is the pattern of syncs is correct, as is the write from the second instruction.

So I think the 6502 is running the correct code, and for some reason the logic analyzer is capturing the data incorrectly.

It looks like data bits 4 and 2 are stuck at one as far as the logic analyzer is concerned:
- A9 -> BD
- 40 -> 54

This is a tool issue, not a beeb issue.

Dave

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 8:21 pm

I think either the Myelin FX board is faulty, or the tube connector is dirty and not making a good connection.

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Elminster
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 8:23 pm

I do have 2 other logic analyzers, and se what they give. But I have to manually hook up each jumper lead, which is painful, so this one seem much easier.

I also have another 40pin tube cable used by the pitube on the master, I could give that a go, in case some sort of cross talk.

And as you say I can also try it on another machine.

Tube connector could be dirty yes, as I have no display I cant really see what it is doing.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 8:28 pm

This very is nearly working... it's just bits 4 and 2 not making proper contact somewhere.

Definitely start by cleaning the tube connector, either with something abrasive, or by plugging/unplugging the cable about 20 times.

Then it will get really interesting and you'll see the value of this over a conventional logic analyzer.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 8:30 pm

hoglet wrote:
Tue Aug 14, 2018 8:21 pm
I think either the Myelin FX board is faulty, or the tube connector is dirty and not making a good connection.
I know pitube on Myelin's board is working in the Electron, but obviously not use the tube connector there.

No thinking about it it must be tarnish. This is the oldest Beeb I own and it broke before pitubedirect came out, so very likely that nothing has ever been plugged into the tube port before on this machine, let alone recently. Will break out the carbon pencil tomorrow.

Edit: This is the one I memory tested with ICE-T. It is also halts after a while, and all the addres lines go high, was interested in see what this one made of it with the decode rather than ICET dump.

Edit2: As you can see from the thread viewtopic.php?f=3&t=9438 I dont have much visual clues to go on. I feel like I am making progress, even f only in understand what tools to use and how to use them.
Last edited by Elminster on Tue Aug 14, 2018 8:41 pm, edited 2 times in total.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 8:56 pm

hoglet wrote:
Tue Aug 14, 2018 8:28 pm
This very is nearly working... it's just bits 4 and 2 not making proper contact somewhere.
I will give it a good clean and pay speacial attention to pins 20 & 16. Be interesting to see if those pins 'look' worse than the others. Probably not.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 9:14 pm

Elminster wrote:
Tue Aug 14, 2018 8:30 pm
Edit2: As you can see from the thread viewtopic.php?f=3&t=9438 I dont have much visual clues to go on. I feel like I am making progress, even f only in understand what tools to use and how to use them.
Yes, but from that thread you say:
Restarted it and goes through power cycle okay. You can type ‘vdu 7’ and it will beep, can type ‘mode <n>’ and the screen will change to a different colour/format of fuzzy.
So actually it seems the 6502/memory/ROMS/6522/interrupts are working perfectly, and the fault is just a video display fault.

You should be able to capture a good trace off the 6502, but I suspect it will be "normal" so won't actually tell you much.

Then again, I could be wrong....

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 9:32 pm

If you leave it wrong a while it will freeze, the trouble you don’t know that cause you can’t see the screen, doing a control break brings it back. I only found this out when I started using a logic probe and a scope. Does the same with logic analyser running live. It stops at the same time scope shows address lines go high.

This could be a second fault or the same fault. So I was interested to see what it was doing when it freezes, hence the logic analyser. It is a bit of an annoyance, as when trace the video ic with probe or scope you think you have found issue only to find it has done the random freeze thing. And doing a control break brings everything back to lift, including what you thought was the fault in the video. Or it could be related in that the fault in the video randomly causes a lockup.

All good fun. Gave your hdmi adaptor a good test, it had a couple of days of displaying rubbish. I have now reconnected BNC and get same issue, need to find RF cable to check that doesn’t work.

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Tue Aug 14, 2018 9:39 pm

Another possibility with a machine like this is to blind type *FX 2,2 and *FX 3,1 then use the serial port to run some tests.

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Re: Open Source Logic Analyzer Experiments

Post by 1024MAK » Tue Aug 14, 2018 9:55 pm

If the 6845 is working (needed to refresh the DRAM), a video fault like you describe should not affect the CPU side of the machine. Most likely two separate faults.

Using the serial port to control the machine is rather fun :D
When I first did this, it took me a couple of attempts to persuade it to go back to using it's own keyboard. This was BSD (before StarDot :lol: ). I was just going on the half a dozen pages of the manual that I had printed off...

Mark
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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Tue Aug 14, 2018 11:09 pm

Now you are throwing another idea at me :)

I want to use the analyser in live run, not to worried if that means get the odd mistake, to see if I can effect it by typing things in. Break works, control g works, but beyond that hard to tell, I used to be able to get the screen to change colour by typing in mode. But that no longer happens.

So I could monitor machine while I type *fx etc.

I have been dong *tape and the load”” but alas no relay click, so I suspect machine may have degraded with second fault, which is confusing me when fixing the original fault.

Edit: currently I leave a scope probe on an arbitrary address line less than 13, and as soon as it gets stuck high I control break and then carry on looking for original issue. Loop.
Last edited by Elminster on Tue Aug 14, 2018 11:16 pm, edited 2 times in total.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Wed Aug 15, 2018 10:32 am

Guessing this is what you want to see, boot vector looks better, not followed the code through yet.

Code: Select all

??? :          : RESET !!       : 7 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
D9CD : A9 40    : LDA #40        : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9CF : 8D 00 0D : STA 0D00       : 4 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D2 : 78       : SEI            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=? I=1 Z=0 C=?
D9D3 : D8       : CLD            : 2 : A=40 X=?? Y=?? SP=?? N=0 V=? D=0 I=1 Z=0 C=?
D9D4 : A2 FF    : LDX #FF        : 2 : A=40 X=FF Y=?? SP=?? N=1 V=? D=0 I=1 Z=0 C=?
D9D6 : 9A       : TXS            : 2 : A=40 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9D7 : AD 4E FE : LDA FE4E       : 4 : A=80 X=FF Y=?? SP=FF N=1 V=? D=0 I=1 Z=0 C=?
D9DA : 0A       : ASL A          : 2 : A=00 X=FF Y=?? SP=FF N=0 V=? D=0 I=1 Z=1 C=1
D9DB : 48       : PHA            : 3 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9DC : F0 09    : BEQ D9E7       : 3 : A=00 X=FF Y=?? SP=FE N=0 V=? D=0 I=1 Z=1 C=1
D9E7 : A2 04    : LDX #04        : 2 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9E9 : 86 01    : STX 01         : 3 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
D9EB : 85 00    : STA 00         : 3 : A=00 X=04 Y=?? SP=FE N=0 V=? D=0 I=1 Z=0 C=1
Edit: And that has also fixed the warnings when running live decoding.
Edit2: Forgot to say, same Beeb but attacked tube connector with carbon fibre pencil and switch cleaner.
Last edited by Elminster on Wed Aug 15, 2018 10:44 am, edited 2 times in total.

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Re: Open Source Logic Analyzer Experiments

Post by dp11 » Wed Aug 15, 2018 10:56 am

That looks much better it matches : http://mdfs.net/Docs/Comp/BBC/OS1-20/D940

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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Aug 15, 2018 11:38 am

Great, the tool is now working....

Can you upload another data.bin trace file?

I have had some success in the past at using diiff to compare to a known-good reference trace.


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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Aug 15, 2018 12:25 pm

Elminster wrote:
Wed Aug 15, 2018 12:12 pm
Yep. How big do you want the fx2pipe set to?
Start with 12M samples, which should be about 6 seconds,

Dave

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Wed Aug 15, 2018 5:07 pm

The site went down just as I clicked reply to this last time.

Here you go.

I did a number of live runs but it never hung in the same area of code. So probably taking trace wont help me, unless there is an obvious difference/error. But was worth a try and certianly I know it all now works.

If I get really bored and run out of idea I migh start working through the trace. But think I shall go bakc to poking at components with multimeters and probes.
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Re: Open Source Logic Analyzer Experiments

Post by hoglet » Wed Aug 15, 2018 5:29 pm

Elminster wrote:
Wed Aug 15, 2018 5:07 pm
I did a number of live runs but it never hung in the same area of code. So probably taking trace wont help me, unless there is an obvious difference/error. But was worth a try and certianly I know it all now works.
There's nothing especially suspicious in the trace. For example, there were no memory failures flagged.

In the end, comparing with my reference trace didn't work, because my reference is from a power up break, where as your trace was from a normal break, so they end up very different (they diverge at instruction 8!)

Dave
Last edited by hoglet on Wed Aug 15, 2018 5:29 pm, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Post by Elminster » Wed Aug 15, 2018 5:36 pm

hoglet wrote:
Wed Aug 15, 2018 5:29 pm
Elminster wrote:
Wed Aug 15, 2018 5:07 pm
I did a number of live runs but it never hung in the same area of code. So probably taking trace wont help me, unless there is an obvious difference/error. But was worth a try and certianly I know it all now works.
There's nothing especially suspicious in the trace. For example, there were no memory failures flagged.

In the end, comparing with my reference trace didn't work, because my reference is from a power up break, where as your trace was from a normal break, so they end up very different (they diverge at instruction 8!)

Dave
Hmmm. By power up break you mean from a switch on? That is what I did. I Set up fx2pipe to captue first and then powered on.I dont think I could have sent the wrong trace as the only non powerup breaks I have traced were live ones and not saved those to a file as piped stright into decode. Or I have misunderstood what you meant.

I can do another one if that helps.
Last edited by Elminster on Wed Aug 15, 2018 5:37 pm, edited 1 time in total.

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