And - Dave you were going to offer some words explaining what the various interrupt conditions mean. I don't think what I've written really covers this as yet.
On the Electron there are five interrupt conditions, each of which has a status flag in &FE00.
- High Tone Detect (Bit 6)
- this interrupt indicates that 10 successive bits of high tone (i.e. 20 cycles of 2400Hz) have been detected on the tape input. It's cleared by setting bit 6 of &FE05. The high tone detection circuity is only enabled when the Motor Control bit in &FE07 is set. For correct operation it also requires the counter mode in &FE07 to be "tape input" and the counter value in &FE06 to be 0 (or close to 0).
- Tx Empty (Bit 5)
- this interrupt indicates a byte has been sent to the tape output and the data shift register is empty and ready for the next byte to be written. It's set immediately after bit 7 of the byte has been sent, and prior to the stop bit being sent. This interrupt is cleared when the next byte is written to the data shift register. It's worth emphasising that the normal state of this interrupt is set, and only whilst a byte is being sent it is ever clear.
- Rx Full (Bit 4)
- this interrupt indicates a byte received from the tape input and is available in the data shift register (&FE04). It's set as soon as bit 7 of the byte has been clocked into the shift register. It's cleared either by reading the shift register, or when the start bit of the next byte is clocked into the shift register. This gives a window for reading the shift register of two bit times, or approximately 1.66ms. This interrupt can be occur spuriously in other counter modes. For example, when switching to tape output mode. Unlike the high tone detect, it's not dependent on the setting of Motor Control bit in &FE07.
- RTC (Bit 3)
- this interrupt occurs at 50Hz and is used (in conjunction with Display End) to implement a 100Hz system clock. It occurs
when the video output reaches line 99 of the active display, but the position within the line varies actually between the odd and even fields. More specifically, the ULA generates this interrupt exactly 8192us after the end of the 160us vertical sync pulse. The interrupt is cleared by setting bit 5 of &FE05.
- Display End (Bit 2)
- this interrupt occurs when the video output reaches the falling edge of the horizontal sync pulse after the last active line of the display. It's cleared by setting bit 4 of &FE05.
Both RTC and Display End occur at 50Hz (every 20ms), but they are staggered by 10ms, and together they are used to generate a 100Hz system clock (used for TIME, etc).
The exact timing of the RTC and Display End interrupts can be seen in the scope pictures in this post, which would be great to include:
http://www.stardot.org.uk/forums/viewto ... 09#p134109