Beeb FPGA

discuss both original and modern hardware for the bbc micro/electron
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fordp
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Re: Beeb FPGA

Post by fordp » Mon Nov 16, 2015 9:59 pm

Well done Dave,

Amazing progress in such a short time. I like your audio hack to avoid aliasing.

Are there any low pass filters to match the BBC circuit or is the output notionally identical to the output of the sound chip?

I expect the sound output will have to mix Sid's, cassette output and M5000's in the fullness of time if there is space in the FPGA.

I hope the scan doubler can be made to work as without that it will limit the appeal of the DE1 core. Are you feeding the sRGB version in to a SCART input or VGA?

The great thing about the DE1 is that it has two totally separate RAM chip so maybe a second processor can be built in with an HDL bootrom and SDRAM memory. The great thing about the second processor is you can run it at any clock rate.

I hope I improve my HDL skills and find time to make the fastest BEEB in history with a Cortex A9 second processor on something like the Zync 7020. This is way beyond my skills at this time however.

All the best.

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Re: Beeb FPGA

Post by fordp » Mon Nov 16, 2015 10:11 pm

hoglet wrote:Any early adopters for the Altera DE1 Build? :D :D :D

---- Snip ------

Have fun, and let me know if you have any problems.....

Dave
Oops just seen this. I will find some time to try this before the weekend and report back.

I may be running my Yatzee game I wrote during the '80s before too long :D

Cheers

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Re: Beeb FPGA

Post by hoglet » Mon Nov 16, 2015 10:24 pm

fordp wrote: Are there any low pass filters to match the BBC circuit or is the output notionally identical to the output of the sound chip?
It's notionally identical to the chip - there are no filters that I'm aware of.
fordp wrote: I expect the sound output will have to mix Sid's, cassette output and M5000's in the fullness of time if there is space in the FPGA.
That did occur to me as well.

At 48Khz asynchronous the sound artefacts are close to in-audible, so that wouldn't be to bad.
fordp wrote: I hope the scan doubler can be made to work as without that it will limit the appeal of the DE1 core.
They seem to be working about as well (or as badly) as on the Papilio.

Have you tried both of them to see which works best? Mode 7 is not great, but the other modes are pretty crisp. By adjusting the CLOCK (or WIDTH) in the monitor you can get close to pixel per perfect.
fordp wrote: Are you feeding the sRGB version in to a SCART input or VGA?
Into SCART on a TV/Monitor - a LG 22NM43D.
fordp wrote: The great thing about the DE1 is that it has two totally separate RAM chip so maybe a second processor can be built in with an HDL bootrom and SDRAM memory. The great thing about the second processor is you can run it at any clock rate.
We have lots of Co Pro's to choose from :D
fordp wrote: I hope I improve my HDL skills and find time to make the fastest BEEB in history with a Cortex A9 second processor on something like the Zync 7020. This is way beyond my skills at this time however.
Good luck!

And thanks again for the board!!!

Dave

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Re: Beeb FPGA

Post by fordp » Mon Nov 16, 2015 10:54 pm

Thanks for the prompt reply.

I am pleased my spare DE1 is no longer gathering dust.

Do not worry about the postage, its on me. It was only the price of a couple of beers anyway.

I look forward to finally preserving some of my old programs and being able to run/ play them again on a sturdy modern piece of kit.

I may have to get my synths out of storage too and have a play both on my real BBC Master and get some HDL going to have Midi on the DE1.

FordP
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Re: Beeb FPGA

Post by PhilYoung » Tue Nov 17, 2015 12:12 pm

hoglet wrote:Any early adopters for the Altera DE1 Build? :D :D :D

Dave
Hi,

I've tried this on my 'new/bad' SRAM' DE1, and it's the same old story I'm sad to say.

It almost works, so I get a display (with some corruption) and can see the different start up screens for BBC B and Master, and the different modes for the BBC selected by the toggle switches and so on. I can enter, list and run short BASIC programs but eventually it freezes up.

I don't think there is any point in your trying to get it going on this broken version of the DE1 that Terasic decided to produce, the problem seems common to several projects and the only viable solution is a RAM swap.

Cheers,

Phil Young

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 12:31 pm

PhilYoung wrote: I've tried this on my 'new/bad' SRAM' DE1, and it's the same old story I'm sad to say.

It almost works, so I get a display (with some corruption) and can see the different start up screens for BBC B and Master, and the different modes for the BBC selected by the toggle switches and so on. I can enter, list and run short BASIC programs but eventually it freezes up.
Can you post a photo of the corruption?

On a VGA monitor the best display is using:
- Select the Mist scan doubler (SW8 in the down position, SW7 in the up position)
- *TV 0,1 followed by break to disable interlace
- select a MODE other then Mode 7
PhilYoung wrote: I don't think there is any point in your trying to get it going on this broken version of the DE1 that Terasic decided to produce, the problem seems common to several projects and the only viable solution is a RAM swap.
Are you up for trying a couple of test builds? :D

There's two specific things I would like to try:
- Gating the memory write signal with a clock
- Reducing the drive on all the FPGA outputs which should reduce noise and cross-talk generally.

The thing is, there's probably lots of these boards out there, and for most people a RAM swap is not a viable thing to do.

Dave

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 12:50 pm

Hi Phil,
PhilYoung wrote:I don't think there is any point in your trying to get it going on this broken version of the DE1 that Terasic decided to produce, the problem seems common to several projects and the only viable solution is a RAM swap.
So, assuming I can persuade you to spend a bit of time on this with me, here are three test builds to try:
BeebFPGAAlteraDE1Test.zip
(376.24 KiB) Downloaded 37 times
Try then all, and see if any of them improve the memory reliability with the EDBLL devices.

Dave

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Re: Beeb FPGA

Post by fordp » Tue Nov 17, 2015 12:58 pm

My DE1's are very old and do not have the SRAM problem I think.

Earlier in this thread (or maybe another thread) you said you were using the RAM at 32Mhz and could maybe clock it down to 4MHz which was of course the speed of the RAM on the actual BBC.

Your idea to gate the control lines is good as it is mentioned elsewhere that the problem is cross-talk. If that is the case slowing down the accesses and delaying asserting the control lines could help.

I suspect others are correct and it is a layout issue. If the tracks are on the outer layers then cut tracks and a bit of tiny coax may fix the issue too. That would be a a bit scary to do however.

It was not long after I got mine that they switched chips I think so there must be a lot of the new type out there :(

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Re: Beeb FPGA

Post by PhilYoung » Tue Nov 17, 2015 1:09 pm

hoglet wrote:
PhilYoung wrote: I've tried this on my 'new/bad' SRAM' DE1, and it's the same old story I'm sad to say.

It almost works, so I get a display (with some corruption) and can see the different start up screens for BBC B and Master, and the different modes for the BBC selected by the toggle switches and so on. I can enter, list and run short BASIC programs but eventually it freezes up.
Can you post a photo of the corruption?

On a VGA monitor the best display is using:
- Select the Mist scan doubler (SW8 in the down position, SW7 in the up position)
- *TV 0,1 followed by break to disable interlace
- select a MODE other then Mode 7
PhilYoung wrote: I don't think there is any point in your trying to get it going on this broken version of the DE1 that Terasic decided to produce, the problem seems common to several projects and the only viable solution is a RAM swap.
Are you up for trying a couple of test builds? :D

There's two specific things I would like to try:
- Gating the memory write signal with a clock
- Reducing the drive on all the FPGA outputs which should reduce noise and cross-talk generally.

The thing is, there's probably lots of these boards out there, and for most people a RAM swap is not a viable thing to do.

Dave
Yes I can certainly try builds you can produce. I suppose all the recent board will have similar problems and it would certainly be easier than the RAM swap option.

I've had the switches set as you suggested, and tried various SW2-0 mode settings. Further info is that as a BBC B it will only boot correctly in Mode7 but works fine in other modes if the mode is manually selected.

Here are a couple of Mode7 shots, you can see that the corruption on screen is quite similar between boots and occasionally changes without any intervention:
DSCF0051_resized.jpg
DSCF0052_resized.jpg
and here is a Mode 3 example.
DSCF0055_resized.jpg
This also often changes without intervention, but only in the areas that are already corrupted.

Hopefully this might give you some clues,

Cheers,

Phil Young

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Re: Beeb FPGA

Post by PhilYoung » Tue Nov 17, 2015 1:38 pm

hoglet wrote:Hi Phil,
PhilYoung wrote:I don't think there is any point in your trying to get it going on this broken version of the DE1 that Terasic decided to produce, the problem seems common to several projects and the only viable solution is a RAM swap.
So, assuming I can persuade you to spend a bit of time on this with me, here are three test builds to try:
BeebFPGAAlteraDE1Test.zip
Try then all, and see if any of them improve the memory reliability with the EDBLL devices.

Dave
Hi,

Posts crossed !

I've just tried these and I think you've got it...

The 'ma' version works fine, boots in various modes, no screen corruption, SD card works. Not tried the sound yet but I've no reason to suppose that doesn't work also.

The 'gc' version fails - screen full of garbage on boot, doesn't respond to the keyboard, sometimes no screen visible at all on boot. So worse than the original really.

The 'gc-ma' version however does work as well as the 'ma' version.

Congratulations !

What is it that these do, I wonder if it might be applicable to other DE1 projects ?

I think Samuel L Jackson (nearly) expresses it best if you substitute 'SRAM' for 'snakes' and 'board' for 'plane'

https://www.youtube.com/watch?v=z4t6zNZ-b0A (TV edit so safe for work and won't frighten the horses)

Cheers,

Phil Young

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 2:19 pm

PhilYoung wrote: I've just tried these and I think you've got it...

The 'ma' version works fine, boots in various modes, no screen corruption, SD card works. Not tried the sound yet but I've no reason to suppose that doesn't work also.

The 'gc' version fails - screen full of garbage on boot, doesn't respond to the keyboard, sometimes no screen visible at all on boot. So worse than the original really.

The 'gc-ma' version however does work as well as the 'ma' version.

Congratulations !

What is it that these do, I wonder if it might be applicable to other DE1 projects ?
What seems to have made a difference is reducing the drive on the FPGA outputs from 24mA (the default) to 4mA.

When an FPGA drives a large number of outputs that all switch at the same time (e.g. an address bus) from the same part of the chip, other near-by outputs that are not meant to change can be affected. This effect is called ground bounce. Internally in the FPGA the ground level will briefly rise, sometimes by several hundred millivolts. Reducing the output current drive massively reduces this effect.

In the Cyclone II data sheet, Altera don't document any limits on the number of simultaneously switching output (SSOs). But they do mention it in passing on page 10-24: http://www.cs.columbia.edu/~sedwards/cl ... cii5v1.pdf

XIlinx are more explicit, and the table below is actually quite frightening:
SSO.png
At 24mA drive (the default in Quartus) the limit can be as low as 2 per bank. Reduce the drive to 4mA, and this increases to 34 per bank.

I strongly suspect this is what's happening here.

Why does this affect the EDBLL RAM more than the earlier RAM? Maybe the input switching thresholds are slightly lower. Maybe the new devices are actually faster, so a glitch on the WE signal becomes more significant. It doesn't matter really, what's important is the solution.

It's good practice in FPGA design to carefully select the output drive current got each output to only as much as is needed to meet timing.

Most people (myself included) don't do this until you actually hit a problem.

I'll commit the _4ma_gc version as a permanent fix, as I believe the SRAM_WEn clock gating is actually beneficial as well.

Dave

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 2:33 pm

Hi Phil,

I've updated the released version with the above changes:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

It would be great if you could re-test this version, to make sure I've not messed anything up.

Thanks!

Dave

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Re: Beeb FPGA

Post by PhilYoung » Tue Nov 17, 2015 3:02 pm

hoglet wrote:Hi Phil,

I've updated the released version with the above changes:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

It would be great if you could re-test this version, to make sure I've not messed anything up.

Thanks!

Dave
Hi Dave,

I've just tested those, both the 'sof' and 'pof' versions. Both are working fine, thanks, no corruption or other problems seen.

The only slight problem is that the SD card I'm using is working fine in 'BBC' mode but is giving me 'Card format?' in 'Master' mode. And I don't have an appropriate RS232 lead to try out the debugger, but I'm sure ebay can help with that,

Cheers,

Phil Young

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 3:20 pm

PhilYoung wrote:The only slight problem is that the SD card I'm using is working fine in 'BBC' mode but is giving me 'Card format?' in 'Master' mode. And I don't have an appropriate RS232 lead to try out the debugger, but I'm sure ebay can help with that,
That's probably because it's FAT-32, and I don't think MMFS (in the Master) supports FAT-32.

Do you have a card you can format with FAT-16?

Dave

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 3:51 pm

IMG_0148.JPG
It sounds pretty good to me!

There's not enough FPGA RAM to include both the SID and the ICE T65 debugger in the Altera build, so for now I've disabled the ICE. These are compile time options, and easy to change.

Dave

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Re: Beeb FPGA

Post by PhilYoung » Tue Nov 17, 2015 4:07 pm

hoglet wrote:
PhilYoung wrote:The only slight problem is that the SD card I'm using is working fine in 'BBC' mode but is giving me 'Card format?' in 'Master' mode. And I don't have an appropriate RS232 lead to try out the debugger, but I'm sure ebay can help with that,
That's probably because it's FAT-32, and I don't think MMFS (in the Master) supports FAT-32.

Do you have a card you can format with FAT-16?

Dave
That was it thanks,

Cheers,

Phil Young

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Re: Beeb FPGA

Post by TheCorfiot » Tue Nov 17, 2015 4:32 pm

Dave, you genius, thanks so much for the DE1 builds.
I will load them up tonight & start testing but from what I have read you have worked wonders.

Thanks so much

Bas :)

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Re: Beeb FPGA

Post by TheCorfiot » Tue Nov 17, 2015 5:53 pm

My DE 1 board has the Good SRAM thankfully...

BUT, using ASP (pof file) I cant get any life out of it, the 7SEG display does not appear to say anything valid either...

I have tried loading the rom image file into flash at both #0 & #20000 (as in Mike sterlings setup) with no change.

I am using the same video cable as I built for Mike's design, CSYNC=VGA HSync...and my switches are all set to zero as I want to use sRGB mode.

Very strange.. I reloaded MIkes design in case it was anything stupid I was doing and that went fine...

HELP !!!

Bas :)

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 6:03 pm

TheCorfiot wrote:My DE 1 board has the Good SRAM thankfully...

BUT, using ASP (pof file) I cant get any life out of it, the 7SEG display does not appear to say anything valid either...

I have tried loading the rom image file into flash at both #0 & #20000 (as in Mike sterlings setup) with no change.

I am using the same video cable as I built for Mike's design, CSYNC=VGA HSync...and my switches are all set to zero as I want to use sRGB mode.

Very strange.. I reloaded MIkes design in case it was anything stupid I was doing and that went fine...

HELP !!!

Bas :)
Can you post a photo of the board please? (powered up!)

A couple of things to try....

Are any red LEDs illuminated?

What's on the HEX display?

Does caps lock change anything?

Does F12 (Break) change anything?

Do you have a serial cable? You could try connecting to the ICE, at 57600 baud.

Which .sof file are you using?

Dave

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 6:22 pm

I'm on a bit of a roll now :D :D :D :D
IMG_0153.JPG
Music 5000 is now pretty much working.

I've not done anything to try to synchronize it's output with the DE1's WM8731 DAC, but it sound pretty good to me.

I did hit any interesting issue....

My Music 5000 uses a true dual-port RAM, with independent clocks (32MHz CPU clock on one side, 6 MHz audio clock on the other). Initially it wouldn't even compile, saying the device/quartus combination didn't support this. After a bit of googling, it seems it can be made to work with:
set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE
It seems there is a serious bug with die revision A of the Cyclone II, that was fixed in later versions.

I'm not sure if my board has such a device.

Is anyone aware of this issue, and whether many DE1's are affected?

I could probably update the design to use a single clock, but it would be a pain to have to do this.

Dave

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Re: Beeb FPGA

Post by TheCorfiot » Tue Nov 17, 2015 6:37 pm

HI Dave

Got it working after doing a wipe of the Flash RAM before programming your File ...

Mode 7 is much better...looks like the real thing.
I know for sure that my board has the older 'good' SRAM from the Amiga FPGA trials I did.

Snapper v1 starts promising but then goes haywire, I'm also getting screen corruption on other games.
Sadly Zalaga bites the dust big time too lol....

Main reason I tried snapper was because it's a favourite but also to check the 6522 issues we had before.

Arcadians also seem to have the flashing cursor on screen at all times too.

Getting there though.

Bas :)


EDIT..... Actually tbh very little runs, Planetoid falls to pieces with screen corruption and M128 Mode will not load anything!!
mmmmm
This DE1 board has worked with every other FPGA project I have pumped into it so I'm pretty sure the hardware is OK.
BTW I'm using the SID enabled pof file. and I have loaded the ROM image into flash at address 0

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 6:53 pm

TheCorfiot wrote: EDIT..... Actually tbh very little runs, Planetoid falls to pieces with screen corruption and M128 Mode will not load anything!!
mmmmm
This DE1 board has worked with every other FPGA project I have pumped into it so I'm pretty sure the hardware is OK.
BTW I'm using the SID enabled pof file. and I have loaded the ROM image into flash at address 0
Hmmmm.....

Zalaga fails on both the DE1 and the Papilio, so lets worry about that later.

Planetoids and Snapper both work fine on my DE1.

Let me have a think.

Could you try this build from yesterday:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

Dave

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Re: Beeb FPGA

Post by richardtoohey » Tue Nov 17, 2015 6:56 pm

hoglet wrote:Zalaga fails on both the DE1 and the Papilio, so lets worry about that later.
Don't know if relevant, but Zalaga uses undocumented opcode(s).

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Re: Beeb FPGA

Post by TheCorfiot » Tue Nov 17, 2015 7:11 pm

hoglet wrote:
TheCorfiot wrote: EDIT..... Actually tbh very little runs, Planetoid falls to pieces with screen corruption and M128 Mode will not load anything!!
mmmmm
This DE1 board has worked with every other FPGA project I have pumped into it so I'm pretty sure the hardware is OK.
BTW I'm using the SID enabled pof file. and I have loaded the ROM image into flash at address 0
Hmmmm.....

Zalaga fails on both the DE1 and the Papilio, so lets worry about that later.

Planetoids and Snapper both work fine on my DE1.

Let me have a think.

Could you try this build from yesterday:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

Dave

Hi Dave, thanks for the prompt reply

I forgot to mention that the sound is all over the place too with the latest release.. like the channels were not in sync.

Flashed with the build you referred me to and it all works perfectly in Model B mode. Arcadians still has the active cursor but the sound is now spot on and no screen or ram corruption is occurring... Perfect.
Still struggling to load anything in Master mode, I'm using a 256MB card formatted to fat, will try a different card..as when it halts loading you cant access the card anymore..

Cheers
Bas :)

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 7:25 pm

TheCorfiot wrote: Flashed with the build you referred me to and it all works perfectly in Model B mode.
Bugger, I was hoping that wouldn't be the case.

It would be great if you could quickly run through the three test builds I did for Phil earlier.

This should provide the data to figure out which of the two SRAM timing changes breaks on your board.
TheCorfiot wrote: Arcadians still has the active cursor but the sound is now spot on and no screen or ram corruption is occurring... Perfect.
Still struggling to load anything in Master mode, I'm using a 256MB card formatted to fat, will try a different card..as when it halts loading you cant access the card anymore..
This won't be a hardware issue, but an MMFS software issue.

This needs to be formatted to FAT-16 I think.

Could you try a newer card? It's possible I broke support for older SD Cards in MMFS.

Dave

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Re: Beeb FPGA

Post by TheCorfiot » Tue Nov 17, 2015 7:53 pm

Hi Dave

We will get to the bottom of it lol...

I have tried about 6 different cards from 256MB to 2GB all formatted to fat16 with various cluster sizes, Model B mode works fine with all combinations but Master mode will not successfully load anything, bombs out with MMC Read error..

I will try the 3 test versions you refer to later and give you my findings..
I am confused though as I thought your board was the same as mine with the older SRAM???

Bas ;)

EDIT..... Sorry but, using the pof file I reported as being OK is having problems with Mode 7 Graphics, ex Acornsoft loading screen.
Getting weirder by the minute doh.

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Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 8:18 pm

TheCorfiot wrote: We will get to the bottom of it lol...
Yes, we will!

Piccies always help, especially where you are talking about screens being messed up.

I'm more worried about a possible memory timing issue than an SD Card issue. The Model B uses Dukkies Smart MMC which is quite well tested against lots of different cards. The Master used my build of MMFS which is not well tested at all! So, lets stick to the Model B for now.

The next step is to run through the different builds I posted for Paul.
- Does it boot without obvious issue.
- Will it run Planetoids?
- Will it run Snapper V1?

Just use the .sof file - no need to program them permanently.

Once we have some more data we can take stock.

Dave

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Re: Beeb FPGA

Post by fordp » Tue Nov 17, 2015 8:50 pm

I just cloned the github repository downloaded Quartus and I get the errors below:

Which is this 6502 debug tool I guess is in a separate repository.

Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Nov 17 20:44:34 2015
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Nov 17 20:44:34 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bbc_micro_de1 -c bbc_micro_de1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 4 design units, including 2 entities, in source file /users/simon/documents/github/beebfpga/src/common/sid/sid_components.vhd
Info (12022): Found design unit 1: pwm_sddac-rtl
Info (12022): Found design unit 2: pwm_sdadc-rtl
Info (12023): Found entity 1: pwm_sddac
Info (12023): Found entity 2: pwm_sdadc
Info (12022): Found design unit 1: pwm_sddac-rtl
Info (12022): Found design unit 2: pwm_sdadc-rtl
Info (12023): Found entity 1: pwm_sddac
Info (12023): Found entity 2: pwm_sdadc
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sid/sid_voice.vhd
Info (12022): Found design unit 1: sid_voice-Behavioral
Info (12023): Found entity 1: sid_voice
Info (12022): Found design unit 1: sid_voice-Behavioral
Info (12023): Found entity 1: sid_voice
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sid/sid_coeffs.vhd
Info (12022): Found design unit 1: sid_coeffs-beh
Info (12023): Found entity 1: sid_coeffs
Info (12022): Found design unit 1: sid_coeffs-beh
Info (12023): Found entity 1: sid_coeffs
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sid/sid_filters.vhd
Info (12022): Found design unit 1: sid_filters-beh
Info (12023): Found entity 1: sid_filters
Info (12022): Found design unit 1: sid_filters-beh
Info (12023): Found entity 1: sid_filters
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sid/sid_6581.vhd
Info (12022): Found design unit 1: sid6581-Behavioral
Info (12023): Found entity 1: sid6581
Info (12022): Found design unit 1: sid6581-Behavioral
Info (12023): Found entity 1: sid6581
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/watchevents.vhd
Info (12022): Found design unit 1: watchevents-SYN
Info (12023): Found entity 1: WatchEvents
Info (12022): Found design unit 1: watchevents-SYN
Info (12023): Found entity 1: WatchEvents
Warning (12019): Can't analyze file -- file ../src/common/AtomBusMon/oho_dy1/OhoPack.vhd is missing
Warning (12019): Can't analyze file -- file ../src/common/AtomBusMon/oho_dy1/Oho_Dy1.vhd is missing
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/xpm9kx16.vhd
Info (12022): Found design unit 1: XPM9Kx16-SYN
Info (12023): Found entity 1: XPM9Kx16
Info (12022): Found design unit 1: XPM9Kx16-SYN
Info (12023): Found entity 1: XPM9Kx16
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/xdm2kx8.vhd
Info (12022): Found design unit 1: XDM2Kx8-RTL
Info (12023): Found entity 1: XDM2Kx8
Info (12022): Found design unit 1: XDM2Kx8-RTL
Info (12023): Found entity 1: XDM2Kx8
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Memory/XMemCompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/ResetGenerator.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/RAMDataReg.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/ExtIRQ_Controller.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/external_mux.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/BusMastCompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/AVR_uC_CompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/uC/AVR8.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/spi_mod/spi_slv_sel.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/spi_mod/spi_mod.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/resync/rsnc_vect.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/resync/rsnc_l_vect.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/resync/rsnc_l_bit.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/resync/rsnc_comp_pack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/resync/rsnc_bit.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/uart.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/Timer_Counter.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/SynchronizerLatch.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/SynchronizerDFF.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/SynchronizerCompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/swap_pins.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Peripheral/portx.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/MemArbAndMux/RAMAdrDcd.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/MemArbAndMux/MemRdMux.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/MemArbAndMux/MemAccessCompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/MemArbAndMux/ArbiterAndMux.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/Resync16b_TCK.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/FrqDiv/FrqDiv.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/reg_file.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/pm_fetch_dec.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/io_reg_file.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/io_adr_dec.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/bit_processor.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/AVR_Core_CompPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/avr_core.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/Core/alu_avr.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/CommonPacks/SynthCtrlPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/CommonPacks/std_library.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/CommonPacks/spi_mod_comp_pack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/CommonPacks/AVRuCPackage.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/AVR8/CommonPacks/avr_adr_pack.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/BusMonCore.vhd is missing
Warning (12019): Can't analyze file -- file ../../AtomBusMon/src/MOS6502CpuMonCore.vhd is missing
Info (12021): Found 2 design units, including 0 entities, in source file /users/simon/documents/github/beebfpga/src/common/t65/t65_pack.vhd
Info (12022): Found design unit 1: T65_Pack
Info (12022): Found design unit 2: T65_Pack-body
Info (12022): Found design unit 1: T65_Pack
Info (12022): Found design unit 2: T65_Pack-body
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/t65/t65_mcode.vhd
Info (12022): Found design unit 1: T65_MCode-rtl
Info (12023): Found entity 1: T65_MCode
Info (12022): Found design unit 1: T65_MCode-rtl
Info (12023): Found entity 1: T65_MCode
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/t65/t65_alu.vhd
Info (12022): Found design unit 1: T65_ALU-rtl
Info (12023): Found entity 1: T65_ALU
Info (12022): Found design unit 1: T65_ALU-rtl
Info (12023): Found entity 1: T65_ALU
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/t65/t65.vhd
Info (12022): Found design unit 1: T65-rtl
Info (12023): Found entity 1: T65
Info (12022): Found design unit 1: T65-rtl
Info (12023): Found entity 1: T65
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_top.vhd
Info (12022): Found design unit 1: sn76489_top-struct
Info (12023): Found entity 1: sn76489_top
Info (12022): Found design unit 1: sn76489_top-struct
Info (12023): Found entity 1: sn76489_top
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_tone.vhd
Info (12022): Found design unit 1: sn76489_tone-rtl
Info (12023): Found entity 1: sn76489_tone
Info (12022): Found design unit 1: sn76489_tone-rtl
Info (12023): Found entity 1: sn76489_tone
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_noise.vhd
Info (12022): Found design unit 1: sn76489_noise-rtl
Info (12023): Found entity 1: sn76489_noise
Info (12022): Found design unit 1: sn76489_noise-rtl
Info (12023): Found entity 1: sn76489_noise
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_latch_ctrl.vhd
Info (12022): Found design unit 1: sn76489_latch_ctrl-rtl
Info (12023): Found entity 1: sn76489_latch_ctrl
Info (12022): Found design unit 1: sn76489_latch_ctrl-rtl
Info (12023): Found entity 1: sn76489_latch_ctrl
Info (12021): Found 1 design units, including 0 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_comp_pack-p.vhd
Info (12022): Found design unit 1: sn76489_comp_pack
Info (12022): Found design unit 1: sn76489_comp_pack
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_clock_div.vhd
Info (12022): Found design unit 1: sn76489_clock_div-rtl
Info (12023): Found entity 1: sn76489_clock_div
Info (12022): Found design unit 1: sn76489_clock_div-rtl
Info (12023): Found entity 1: sn76489_clock_div
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/sn76489-1.0/sn76489_attenuator.vhd
Info (12022): Found design unit 1: sn76489_attenuator-rtl
Info (12023): Found entity 1: sn76489_attenuator
Info (12022): Found design unit 1: sn76489_attenuator-rtl
Info (12023): Found entity 1: sn76489_attenuator
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/scandoubler/rgb2vga_scandoubler.vhd
Info (12022): Found design unit 1: rgb2vga_scandoubler-rtl
Info (12023): Found entity 1: rgb2vga_scandoubler
Info (12022): Found design unit 1: rgb2vga_scandoubler-rtl
Info (12023): Found entity 1: rgb2vga_scandoubler
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/scandoubler/rgb2vga_dpram.vhd
Info (12022): Found design unit 1: rgb2vga_dpram-behavioral
Info (12023): Found entity 1: rgb2vga_dpram
Info (12022): Found design unit 1: rgb2vga_dpram-behavioral
Info (12023): Found entity 1: rgb2vga_dpram
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/scandoubler/mist_scandoubler.vhd
Info (12022): Found design unit 1: mist_scandoubler-rtl
Info (12023): Found entity 1: mist_scandoubler
Info (12022): Found design unit 1: mist_scandoubler-rtl
Info (12023): Found entity 1: mist_scandoubler
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/aland/r65cx2.vhd
Info (12022): Found design unit 1: R65C02-Behavioral
Info (12023): Found entity 1: R65C02
Info (12022): Found design unit 1: R65C02-Behavioral
Info (12023): Found entity 1: R65C02
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/vidproc.vhd
Info (12022): Found design unit 1: vidproc-rtl
Info (12023): Found entity 1: vidproc
Info (12022): Found design unit 1: vidproc-rtl
Info (12023): Found entity 1: vidproc
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/upd7002.vhd
Info (12022): Found design unit 1: upd7002-rtl
Info (12023): Found entity 1: upd7002
Info (12022): Found design unit 1: upd7002-rtl
Info (12023): Found entity 1: upd7002
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/saa5050.vhd
Info (12022): Found design unit 1: saa5050-rtl
Info (12023): Found entity 1: saa5050
Info (12022): Found design unit 1: saa5050-rtl
Info (12023): Found entity 1: saa5050
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/saa5050_rom_dual_port.vhd
Info (12022): Found design unit 1: saa5050_rom_dual_port-SYN
Info (12023): Found entity 1: saa5050_rom_dual_port
Info (12022): Found design unit 1: saa5050_rom_dual_port-SYN
Info (12023): Found entity 1: saa5050_rom_dual_port
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/rtc.vhd
Info (12022): Found design unit 1: rtc-rtl
Info (12023): Found entity 1: rtc
Info (12022): Found design unit 1: rtc-rtl
Info (12023): Found entity 1: rtc
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/ps2_intf.vhd
Info (12022): Found design unit 1: ps2_intf-ps2_intf_arch
Info (12023): Found entity 1: ps2_intf
Info (12022): Found design unit 1: ps2_intf-ps2_intf_arch
Info (12023): Found entity 1: ps2_intf
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/mc6845.vhd
Info (12022): Found design unit 1: mc6845-rtl
Info (12023): Found entity 1: mc6845
Info (12022): Found design unit 1: mc6845-rtl
Info (12023): Found entity 1: mc6845
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/m6522.vhd
Info (12022): Found design unit 1: M6522-RTL
Info (12023): Found entity 1: M6522
Info (12022): Found design unit 1: M6522-RTL
Info (12023): Found entity 1: M6522
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/keyboard.vhd
Info (12022): Found design unit 1: keyboard-rtl
Info (12023): Found entity 1: keyboard
Info (12022): Found design unit 1: keyboard-rtl
Info (12023): Found entity 1: keyboard
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/common/bbc_micro_core.vhd
Info (12022): Found design unit 1: bbc_micro_core-rtl
Info (12023): Found entity 1: bbc_micro_core
Info (12022): Found design unit 1: bbc_micro_core-rtl
Info (12023): Found entity 1: bbc_micro_core
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/pll32.vhd
Info (12022): Found design unit 1: pll32-SYN
Info (12023): Found entity 1: pll32
Info (12022): Found design unit 1: pll32-SYN
Info (12023): Found entity 1: pll32
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/i2s_intf.vhd
Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch
Info (12023): Found entity 1: i2s_intf
Info (12022): Found design unit 1: i2s_intf-i2s_intf_arch
Info (12023): Found entity 1: i2s_intf
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/i2c_loader.vhd
Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch
Info (12023): Found entity 1: i2c_loader
Info (12022): Found design unit 1: i2c_loader-i2c_loader_arch
Info (12023): Found entity 1: i2c_loader
Info (12021): Found 2 design units, including 1 entities, in source file /users/simon/documents/github/beebfpga/src/altera/bbc_micro_de1.vhd
Info (12022): Found design unit 1: bbc_micro_de1-rtl
Info (12023): Found entity 1: bbc_micro_de1
Info (12022): Found design unit 1: bbc_micro_de1-rtl
Info (12023): Found entity 1: bbc_micro_de1
Error (10481): VHDL Use Clause error at XDM2Kx8.vhd(5): design library "work" does not contain primary unit "SynthCtrlPack"
Error (10800): VHDL error at XDM2Kx8.vhd(5): selected name in use clause is not an expanded name
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 58 warnings
Error: Peak virtual memory: 508 megabytes
Error: Processing ended: Tue Nov 17 20:44:37 2015
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:02
Error: Peak virtual memory: 508 megabytes
Error: Processing ended: Tue Nov 17 20:44:37 2015
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:02
-----------------------------------------------------------
I am making progress I guess.

FordP
FordP (Simon Ellwood)
Time is an illusion. Lunchtime, doubly so!

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hoglet
Posts: 9584
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Tue Nov 17, 2015 9:02 pm

fordp wrote:I just cloned the github repository downloaded Quartus and I get the errors below:

Which is this 6502 debug tool I guess is in a separate repository.
I haven't worked out how to make this transparent yet in git.

For now, you need to git clone :
https://github.com/hoglet67/AtomBusMon
along side BeebFpga (so they both have the same parent directory).

On Linux I create a sym link in BeebFpga/src/common:
AtomBusMon -> ../../../AtomBusMon/src/

On windows you will have to just create a directory in BeebFpga/src/common called AtomBusMon and copy the files from the src directory of the AtomBusMon project into it.

Dave

User avatar
fordp
Posts: 1101
Joined: Sun Feb 12, 2012 9:08 pm
Location: Peterborough, England
Contact:

Re: Beeb FPGA

Post by fordp » Tue Nov 17, 2015 9:10 pm

Hi Dave,

I have cloned a few repositories now :D

but it looks like AtomBusMon/oho_dy1/OhoPack.vhd and AtomBusMon/oho_dy1/Oho_Dy1.vhd are missing!

FordP
FordP (Simon Ellwood)
Time is an illusion. Lunchtime, doubly so!

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