Beeb FPGA

discuss both original and modern hardware for the bbc micro/electron
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fordp
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Midi Info

Post by fordp » Thu Nov 12, 2015 9:00 am

Hi,

Here is what you need to know for BBC Midi:
Electronics: http://www.midi.org/techspecs/ca33.pdf
Old Interface : http://mdfs.net/Info/Comp/BBC/MIDI/jgh1.gif

fordp
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Re: Beeb FPGA

Post by 1024MAK » Thu Nov 12, 2015 10:25 am

For experimentation and hobby use. If your device already has the power supply to the circuitry free of mains earth (the mains earth is NOT connected to the PSU 0V/common/negative or indeed the positive rails), and you are only using a one direction MIDI link (e.g. MIDI in - receive only), you don't need an opto-isolator / opto-coupler. A suitable small signal NPN transistor will do just fine.

Also working links have been made between normal serial ports and MIDI ports in the past (but not by me, sorry, I don't have details). The hardest part with this is finding suitable settings to program the UART (or similar) chip to get the correct transmission (baud) rate.

Mark

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hoglet
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Re: Beeb FPGA

Post by hoglet » Thu Nov 12, 2015 2:20 pm

1024MAK wrote: Also working links have been made between normal serial ports and MIDI ports in the past (but not by me, sorry, I don't have details). The hardest part with this is finding suitable settings to program the UART (or similar) chip to get the correct transmission (baud) rate.
Here's an example:
http://www.compuphase.com/electronics/midi_rs232.htm

Dave

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Re: Beeb FPGA

Post by fordp » Thu Nov 12, 2015 2:28 pm

Hi All,

Following the official recommended circuit is very cheap especially compared to the cost of my Midi modules and Synths ;)

Retro Computing/ Computer Preservation is my hobby, but I have worked in the Electronic industry for 27 years, so I know that cutting corners can come back and bite you!

Cheers.

FordP
Last edited by fordp on Thu Nov 12, 2015 3:48 pm, edited 2 times in total.
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Re: Beeb FPGA

Post by 1024MAK » Thu Nov 12, 2015 2:51 pm

On StarDot, some members do more than cut corners, they cut whole boards in half :lol:
(See the Atom section, if you dare...)

Mark

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Re: Beeb FPGA

Post by fordp » Thu Nov 12, 2015 11:29 pm

1024MAK wrote:The hardest part with this is finding suitable settings to program the UART (or similar) chip to get the correct transmission (baud) rate.

Mark
This is not hard on an FPGA as you know you want 31250 baud this is super simple to generate.
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Re: Beeb FPGA

Post by 1024MAK » Fri Nov 13, 2015 10:10 am

fordp wrote:
1024MAK wrote:The hardest part with this is finding suitable settings to program the UART (or similar) chip to get the correct transmission (baud) rate.
This is not hard on an FPGA as you know you want 31250 baud this is super simple to generate.
Yes, true. But if you are say, using an existing computer's RS232, RS422 or RS423 serial port (or even a TTL level serial port), the UART (or equivalent) is normally programmed by the OS. And the clock signal to it is normally designed to provide RS232, RS422 or RS423 baud rates. So if you want to get it to talk to a proper MIDI IN port, you have to find a clock divider / baud rate setting that is close enough so that the MIDI IN UART (or equivalent) does not suffer from bit errors (under-run or over-run).

Mark

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Re: Beeb FPGA

Post by hoglet » Fri Nov 13, 2015 8:50 pm

Hi Guys,

I've done a lot of work today re-working the project to be able to support the Altera DE1 as well as the Papilio Duo, and have the two share a common core.

This is what I ended up with in the core:
https://github.com/hoglet67/BeebFpga/bl ... o_core.vhd

And here are the top level board specific wrappers:
https://github.com/hoglet67/BeebFpga/bl ... ro_duo.vhd
https://github.com/hoglet67/BeebFpga/bl ... ro_de1.vhd

Lots has changed, including the names of the top level projects.

I've been learning my way around the Altera Quartus II tools and on the whole I like them. At the moment I can build the design, and it comfortably meets timing, but memory is a bit tight. The 2C20 only has 52KB compared to the 64KB of the Xilinx XC6SLX9. The ICE T65 takes up 40K. But is does all fit, which is all that matters at the end of the day. It also seems to comfortably meet timing, assuming I have specified all the clock correctly.

As an added bonus, in the re factoring I changed the Master/Beeb mode selection from being a compile time option, to being a run time option set with a jumper. This should make it much easier to switch back and to between the two systems without re-programming. I've re-organized the ROM images so that both sets of ROMs can be included at the same time.

FordP (Simon) is going to send me his spare board so hopefully next week I'll be able to start debugging - I can guarantee it won't work first time. I can't wait now to try it out....

Dave
Last edited by hoglet on Fri Nov 13, 2015 8:54 pm, edited 1 time in total.

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Re: Beeb FPGA

Post by flynnjs » Fri Nov 13, 2015 8:54 pm

Nice work Dave.
I might try to port to DE0nano if I get some time.

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Re: Beeb FPGA

Post by hoglet » Fri Nov 13, 2015 9:07 pm

flynnjs wrote:Nice work Dave.
I might try to port to DE0nano if I get some time.
I'm not sure how well the external memory system would map across. At the moment it needs:
- 512KB of fast external SRAM, or
- 128KB of fast external SRAM and 384KB of external Parallel FLASH ROM

On the DE0 Nano I think the external SDRAM would be too slow, unless you know differently.

There is more internal RAM - 126KB I think, so a Model B should be possible (32K RAM + 64K ROM) would fit, but you would have to drop the ICE.

Dave

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Re: Beeb FPGA

Post by fordp » Fri Nov 13, 2015 9:19 pm

DE1 dispatched today as promised!
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Re: Beeb FPGA

Post by hoglet » Fri Nov 13, 2015 9:28 pm

fordp wrote:DE1 dispatched today as promised!
=D> =D> =D> =D> =D>

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Re: Beeb FPGA

Post by flynnjs » Fri Nov 13, 2015 9:34 pm

I was aware of that. I was thinking internal RAM but I also have a small SRAM daughter card
which fits the Altera standard 40p header which is also found on the boards from eBay eepizza.
This header will also be present on my series 7 development which I hope to have ready in
January.

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Re: Beeb FPGA

Post by jgharston » Fri Nov 13, 2015 10:08 pm

hoglet wrote:Anyway, many hours later, it now looks correct:
IMG_0127.JPG
Time for a glass of wine!
Well done!
hoglet wrote:Question - are there any archives of BBC Teletext Pages in .SSD format anywhere that I could use to do more testing with. I seem to remember some people (BeebMaster?) collecting a load before CeeFax was shut down.
Archives of teletext pages: http://mdfs.net/System/Teletext/

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.32
(C) Copyright J.G.Harston 1989,2005-2020
>_

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Re: Beeb FPGA

Post by flynnjs » Sat Nov 14, 2015 9:36 am

fordp wrote: Econet should be easy too. Just two RS485 drivers needed on the FPGA and the econet chip in HDL.
It's a bit more than that, you need the op-amp and resistors to do it well.

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Re: Beeb FPGA

Post by TheCorfiot » Sat Nov 14, 2015 11:19 am

Thanks so much gor the DE1 ports Dave, cant wait to try them. :)
Video out is VGA i take it?

:)

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Re: Beeb FPGA

Post by hoglet » Sat Nov 14, 2015 11:28 am

TheCorfiot wrote:Thanks so much gor the DE1 ports Dave, cant wait to try them. :)
Video out is VGA i take it?
You have a choice between 800x600 VGA (at 50Hz, so you need a compatible monitor) or sRGB (identical to what the Beeb would send out of it's RGB connector).

In mode 7, sRGB is noticeably better, because a simple line doubler doesn't work well with interlaces signals.

Dave

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Re: Beeb FPGA

Post by fordp » Sat Nov 14, 2015 12:47 pm

flynnjs wrote:
fordp wrote: Econet should be easy too. Just two RS485 drivers needed on the FPGA and the econet chip in HDL.
It's a bit more than that, you need the op-amp and resistors to do it well.
I am no expert. This was a bit of guess work after looking at the beeb circuit diagram. It looked like the drivers were similar enough to a modern RS 485 driver that it would work. The second driver was for the clock that could be either an input or an output without much effort. I will do some more reading and try and learn more.

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Re: Beeb FPGA

Post by grannyg » Sat Nov 14, 2015 1:40 pm

hoglet wrote: If you (or anyone else) want to build this yourself, I can try to improve this a bit, as the ICE-T65 firmware is quite stable to I could check in a binary.
I've now managed to build a bit file from scratch after your latest changes. Starts up as a BBC Micro OK. :D

My monitor has problems with the screen resolution used 720x576@50Hz. It jitters up and down. A lot of games end up in 1440x244@50Hz.
Is it possible to implement something similar to Electron Fpga which has a choice of three.

Also games with speech result in high pitched white noise. e.g. Citadel, Repton 3.

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Re: Beeb FPGA

Post by hoglet » Sat Nov 14, 2015 2:51 pm

grannyg wrote:
hoglet wrote: If you (or anyone else) want to build this yourself, I can try to improve this a bit, as the ICE-T65 firmware is quite stable to I could check in a binary.
I've now managed to build a bit file from scratch after your latest changes. Starts up as a BBC Micro OK. :D

My monitor has problems with the screen resolution used 720x576@50Hz. It jitters up and down. A lot of games end up in 1440x244@50Hz.
Is it possible to implement something similar to Electron Fpga which has a choice of three.
What monitor are you using?

What jumpers do you have fitted on the header block on the Classic Computing Shield?

The settings are as follows:
- DIP 0 - VGA output when fitted, sRGB output when missing
- DIP 1 - RGB2VGA scan doubler when fitted, Mist scan doubler when missing (only valid when in VGA mode)
- DIP 2 - Master when fitted, BBC B when missing

DIP 0 is nearest to the PS/2 connector.

Dave

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Re: Beeb FPGA

Post by Wombatter » Sat Nov 14, 2015 6:02 pm

HI all, can someone tell me how to get this working with the MIST cores....

With FAT32 card core stops at SuperMMC prompt, with FAT16 card core does not even load, FAT32 & FAT16 dual parition card same hang at SuperMMC prompt.. what am I missing? even tried with the rom files on the card as well, even though theyre in the core file.

It's a working beeb.mmc file that I use, seen videos of it running but i can't getting it running here :( driving me nuts lol..


Al.

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Re: Beeb FPGA

Post by hoglet » Sat Nov 14, 2015 6:10 pm

Wombatter wrote: With FAT32 card core stops at SuperMMC prompt, with FAT16 card core does not even load, FAT32 & FAT16 dual parition card same hang at SuperMMC prompt.. what am I missing? even tried with the rom files on the card as well, even though theyre in the core file.

It's a working beeb.mmc file that I use, seen videos of it running but i can't getting it running here :( driving me nuts lol..)
The SuperMMC used by the Mist core has several restrictions :
- Only support older SDCARDs, not more recent SDHC cards
- Only supports FAT16 file system (I think)
- BEEB.MMB file must be in the first eight directory entries on the first partition

You need to try to find a old SDCARD wih say 512MB or 1GB capacity. Larger cards will likely be SDHC.

Posting a screen shot of exactly how it hangs might also give some clues.

Dave

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Re: Beeb FPGA

Post by Wombatter » Sat Nov 14, 2015 6:36 pm

Thanks, i finally figured it out, didnt have any old cards, so did 256MB fat16 partition on my 4GB card and worked ok :)

Have to say the sound/audio routines need work, but runs good otherwise :) :thumbsup:


Al

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Re: Beeb FPGA

Post by hoglet » Sat Nov 14, 2015 7:40 pm

Wombatter wrote:Thanks, i finally figured it out, didnt have any old cards, so did 256MB fat16 partition on my 4GB card and worked ok :)

Have to say the sound/audio routines need work, but runs good otherwise :) :thumbsup:

Al
If you are using the Mist cores, then I have nothing to do with them. You need to thank Till Harbaum, or send bugs his way. :D

Dave

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Re: Beeb FPGA

Post by grannyg » Sat Nov 14, 2015 7:58 pm

hoglet wrote: The settings are as follows:
- DIP 0 - VGA output when fitted, sRGB output when missing
- DIP 1 - RGB2VGA scan doubler when fitted, Mist scan doubler when missing (only valid when in VGA mode)
- DIP 2 - Master when fitted, BBC B when missing

DIP 0 is nearest to the PS/2 connector.
Thanks. DIP 0 was the missing link. :idea:
The monitor is a Viewsonic VP2770-LED which is a bit fussy about what it can display.

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Re: Beeb FPGA

Post by hoglet » Mon Nov 16, 2015 11:33 am

:D :D :D :D :D :D :D :D :D
IMG_0145.JPG
There appears to be no data in the SAA5050 character set ROM, which should be easy to fix.

More updates soon.....

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Re: Beeb FPGA

Post by hoglet » Mon Nov 16, 2015 12:11 pm

Things that are looking good....

- SAA5050 Character ROM now fixed.
- ICE-T65 is working.
- Beeb and Master both seem happy
- MMC interface working
- Master Elite runs
- Planetoids runs
- sRGB video output (like the original Beeb) looks great

Things that are not so good....
- Sound is a bit rough.
- Scan doubler seems a bit messed up, very juddery

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Re: Beeb FPGA

Post by hoglet » Mon Nov 16, 2015 6:27 pm

Sorry for the long post - I wanted to write this down before I forgot it.

I've been messing with the audio all afternoon.

The core problem is that the audio sounds "rough", i.e. if you do a control^G then it's mostly a single tone, but other artefacts are obviously present.

The Altera DE1 contains a high quality Wolfson WM8731 DAC:
http://www.cs.columbia.edu/~sedwards/cl ... -CODEC.pdf

Surprising, in its' current configuration it's much worse than on the Papilio Duo, which used a "DIY" 1-bit delta-sigma convertor DAC, and an external R/C network.

Here's what I think is happening...

The SN76489 is basically putting out a perfect square wave, the frequency of which is 125,000 / N. So for example, I think for ^G the value of N is 240, giving a frequency of 520.8Hz, and a cycle time of exactly 240 * 8us = 1,920us.

If you looked at the DAC output, it was became clear what was happening. Although the output was a square wave at the correct frequency, there was jitter in the edges, and the amount of that jitter was += 1/Fs (i.e. the sample rate of the DAC).

Here in lies the fundamental problem.... The DAC is being fed with an synchronous 12MHz clock, and this s divided down by 250 to give a sample rate of exactly 48KHz, which is once every 20.8333us. With this configuration, jitter is inevitable, because 20.83333 does not divide nicely into 1,920.

To get this to work perfectly, I think there are two approaches:
- use DSP to perform sample rate conversion correctly
- somehow synchronize the DAC to the audio source

I've been experimenting with the latter.

I've put the DAC into a mode where:
- it expects a 12.288MHz clock
- the internal divider is set to 128
- so the notional Fs is 96KHz

Now the sneaky trick.. Instead of feeing it 12.288MHz, I've fed it 16MHz, which raises the sampling frequency to 125KHz.

Which is synchronous to the SN76489.

With this setting, audio is much much better.

Dave

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Re: Beeb FPGA

Post by leenew » Mon Nov 16, 2015 6:54 pm

=D> Excellent! =D>

Lee.

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Re: Beeb FPGA

Post by hoglet » Mon Nov 16, 2015 6:54 pm

Any early adopters for the Altera DE1 Build? :D :D :D

I've checked my current binary build into git:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

Here are the steps you need to take:

1. Obtain a BEEB.MMB file with some games on.

I think I'm using this one:
http://www.retrocomputers.eu/bbc/BEEB.zip

Format an SD Card as FAT-16 and write this file to it.

It's possible FAT-32 would work, I just haven't tested this yet.

2. Program rom_image.bin into the FLASH.

This can be done using the Altera Control Panel app, which only runs on a Windows PC. Follow the documentation in the user guide for doing this:
ftp://ftp.altera.com/up/pub/Altera_Mate ... Manual.pdf

3. Set the DE1 slide switches appropriately:

The key switches are as follows:
SW9 - down BBC B, up Master 128
SW8 - down Mist Scan Doubler for VGA, up RGBtoVGA Scan Doubler for VGA
SW7 - down 15.875KHz sRGB; up 31.5KHz VGa
SW6 - unused
SW5 - unused
SW4 - BBC B DIP 4
SW3 - BBC B DIP 3
SW2 - BBC B DIP 2 - Screen Mode
SW1 - BBC B DIP 1 - Screen Mode
SW0 - BBC B DIP 0 - Screen Mode

If you are using a sRGB monitor, connect the Composite Sync input to the VGA HSync output.

4. Program the bbc_micro_de1.sof into the Altera FPGA using the Programmer tool and the built-in USB blaster.

Note, with the .sof file the configuration will be lost when the system is powered off. I haven't yet tried programming this .pof file into persistant configuration.

5. Press Key0 on the DE1 to reset (if necessary)

The HEX display is the current processor address (actually backwards, which I'll fix in the next build).

LEDR0 is the Caps Lock LED and LEDR2 is the Shift Lock LED.

If you hook up a Serial Cable at 57,600 baud you should be able to run the ICE-T65 debugger. Hit return to get into this.

Have fun, and let me know if you have any problems.....

Dave

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