Beeb FPGA

[adrm]

I do notice that MODE 7 text is no better than on the DE2.
I thought the DE1's "simpler" circuitry would give a better result, but maybe I misunderstood?

Ok, here's Hoglet's statement on this:

One more thing... Mode 7 when using sRGB mode to a SCART TV looks perfect, and is indistinguishable from a real Beeb:

This was possibly explained in the past (if so, sorry), but how do I get sRGB mode on the DE1?

[hoglet]

This was possibly explained in the past (if so, sorry), but how do I get sRGB mode on the DE1?

Switch 7 and 8 in the down position.

Then you need a VGA to SCART cable, and Hsync on VGA connected to Composite Sync on SCART.

(Very few VGA monitors will work at 15.625KHz line frequency).

[crj]

More likely the USB keyboard doesn't support PS/2 mode, or the PS/2 adapter is a mouse adapter, not a keyboard adapter.

Mmm. There's no reason to believe a keyboard with a USB A plug can also do PS/2 unless it came with an adapter.

If you do use some random adapter you have lying around, make sure it's purple and/or with a keyboard symbol moulded into it, rather than green and/or with a mouse symbol.

The only general purpose adapter I know of that allows you to plug USB keyboards and mice into PS/2 computers is the Adder KMU2P. It's the best part of a hundred quid.

[adrm]

I'm sure what you guys say is true in general.
However, it seems I've been lucky.

The following items work fine with both my DE1 and the DE2:

• Cheapo Advent USB keyboard
• Random green, i.e. for mouse, USB to PS/2 adapter

Will these play nice forever?
Only time will tell. Thing is; it's getting harder to find PS/2 keyboards these days. Next to impossible to pick up in local shops here, afaik.

[adrm]

This was possibly explained in the past (if so, sorry), but how do I get sRGB mode on the DE1?

Switch 7 and 8 in the down position.

Then you need a VGA to SCART cable, and Hsync on VGA connected to Composite Sync on SCART.

(Very few VGA monitors will work at 15.625KHz line frequency).

Thanks.

Given the lack of SCART inputs in my current screens, and reluctance to add yet another unit just for this purpose, I think I'll pass on the idea after all.

I guess I could try getting the VGA->SCART cable and try running it through my excellent SCART->HDMI converter box, but I'm guessing this will be a bit of a hit or miss prospect.

[fordp]

My TV works at both TV and VGA rates through the VGA input. I then use the Scart input for my real Beebs.

[Coeus]

The above disk image has an edited RUNNER script with the lines that load the M2 and M4 modules removed. These modules hang if the Music 2000 and Music 4000 hardware is not present. This happens on real hardware as well, see this and this.

So this would be the version I got from you in connection with M5000 in B-Em. Interestingly, when I went to implement M4000 emulation in B-Em it was the presence or absence of the actually keyboard that was causing the issue but that the emulated VIA didn't emulate the shift register.

Interestingly, the M500 version, AMPLE BCE, seems to probe for the keyboard anyway rather than having a loadable module which explains why I sometimes got get bad card errors with MMFS after using it.

[Higgy]

Hi hoglet - I've not been around for quite some time (you last helped on the Castle Quest fix).

I finally got around to looking at updating the main MMB with the fixed Uridium, and I was adding 'White Light' (although I need to contact Retro Software to check it is ok).
On my White Light test with ZX Uno (BBC v1.3 Core) I noticed that if you die the screen just goes back and hangs. You don't get a 'Game Over' or High Score.
On the MiST you get the Game Over, but the scrolling is very jerky and there are screen glitches on title etc screens.

How does it run on your FPGA setup?

Thanks

[hoglet]

How does it run on your FPGA setup?

It runs very smoothly, but I get the hang/black screen as well at the end.

I've also just tried on my real Beeb, and that also gets the hang/black screen.

I think it's likely the problem is a memory conflict of some sort between White Light and MMFS.

I'll see if I can find out what this is.

[slingshot]

Hi!

I'm new to this forum, and just want to ask about SDRAM support in BeebFpga. I want to port it to the MiST board, which already has a port of an older version by Mike Stirling. The MiST doesn't have enough BRAM or any SRAM, but has a big SDRAM, so it would be perfect for the core. However during the port, I discovered that the signals for the external mermory are not really SDRAM friendly.
So the questions are:
- are they really need to be delayed one cycle (not a big problem, just I feel it's not necessary)?
- would there any problem with the video if only crtc enable cycles are used for RAM reading? Reading in every other cycle is not really possible with the SDRAM.

[hoglet]

I'm new to this forum, and just want to ask about SDRAM support in BeebFpga.

One additional feature, the 4MHz 6502 Co Processor, relies on being able to squeeze in additional accesses to the external RAM. I just don't think this is going to be possible with SDRAM.

There are some notes about this in the code:
https://github.com/hoglet67/BeebFpga/bl ... .vhd#L1078

Now, the current layout is far from optimal, for example I don't think every other cycle needs to be a video cycle. But still, I think it will be hard to get this working with SDRAM without loosing the Co Processor.

Dave

[slingshot]

Now, the current layout is far from optimal, for example I don't think every other cycle needs to be a video cycle. But still, I think it will be hard to get this working with SDRAM without loosing the Co Processor.

Dave

Thanks for the answer, I saw the co-processor, just I didn't consider this as a must-have. Working B and Master are my first goals.

[fordp]

I'm new to this forum, and just want to ask about SDRAM support in BeebFpga.

One additional feature, the 4MHz 6502 Co Processor, relies on being able to squeeze in additional accesses to the external RAM. I just don't think this is going to be possible with SDRAM.

There are some notes about this in the code:
https://github.com/hoglet67/BeebFpga/bl ... .vhd#L1078

Now, the current layout is far from optimal, for example I don't think every other cycle needs to be a video cycle. But still, I think it will be hard to get this working with SDRAM without loosing the Co Processor.

Dave

The CoPro RAM could be in the SDRAM while the beebs 32K was placed in BlockRAM ?

[dominicbeesley]

What speed is the SRAM running at. I'd have to have a proper dig through my archive but my implementation of a BBC on an FPGA used SDRAM on the DE0 nano. I think I had it running at 8MHz, I can't remember what speed though.

It was certainly servicing the memory requests at 4MHz (the speed the beeb's real RAM runs at for interleaving with the display) to get the processor to run at 4MHz you might be able to do something funky and have the SDRAM run only at 6MHz?

...Quickly looking at the (horrible my first VHDL) code it looks like it was running at 8MHz but with 1/2 the cycles taken up for refreshes you might be able to do away with two of the refreshes? Or you can arrange for the screen accesses to do the refreshing?

D

[Nico24]

Hi - I have just loaded the BBC core onto the MIST fpga board. I don't seem to get the cool rounded BBC font. Does anyone know how I might be able to rectify this?

Thanks in advance!

[hoglet]

Hi - I have just loaded the BBC core onto the MIST fpga board. I don't seem to get the cool rounded BBC font. Does anyone know how I might be able to rectify this?

There are several different BBC Cores in existence. They all build on Mike Stirling's original work, but have gone in different directions, have different features, and run on different hardware.

The "BeebFPGA" core (that this thread is about) is the one that I maintain, and it's here I implemented character rounding (in 2015) and VideoNuLA (2018).

These features don't exist in the MIST BBC Core (written by Stephen Leary).

If you are an FPGA developer then porting might be possible, but it's quite a lot of work, as MIST has different memory timings constraints (being DRAM based).

So sorry, but there's not an easy fix.

Dave