Beeb FPGA

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adrm
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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 9:21 am

hoglet wrote: One more thing... Mode 7 when using sRGB mode to a SCART TV looks perfect, and is indistinguishable from a real Beeb:

Mode 7, resampled to VGA by the scan doubler, looks not so great!

Some of the uprights, e.g. the on the M, end up different widths. This is caused by resampling the 12MHz teletext pixels with a 32MHz VGA clock.

Dave
Dave, I just noticed something interesting about this.

When I first power on and program the board, I see what you describe, i.e. variable width uprights.

If I then, do a hard reset using SW[0] the MODE 7 display gets a lot better, i.e. uprights are the same widths.
Sound promising?
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hoglet
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 9:30 am

adrm wrote: If I then, do a hard reset using SW[0] the MODE 7 display gets a lot better, i.e. uprights are the same widths.
Sound promising?
I've seen something similar. I think this is because there are two possible phases of the 24MHz clock. A suspect it's just moving the problem to different column positions.

The other thing is that the VGA monitor also has a big impact, and can introduce it's own artefacts. I've tried about 6 monitors, and they all look a bit different.

What VGA resolution does your monitor thing the signal is?

By the way, did you try building with any of the interesting extensions, like the 65C02 Second Processor, or the SID, or the Music 5000? Lots of fun to be had there....

e.g.

Code: Select all

        generic map (
            IncludeAMXMouse    => false,
            IncludeSID         => true,
            IncludeMusic5000   => true,
            IncludeICEDebugger => false,
            IncludeCoPro6502   => true,
            IncludeCoProSPI    => false,
            UseOrigKeyboard    => false,
            UseT65Core         => false,
            UseAlanDCore       => true
            )
(In the DE1 there's not space for them all at the same time, but the DE2 might be different)

There's also Master 128 mode (SW 9 up I think)

Dave

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adrm
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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 9:39 am

hoglet wrote:
What VGA resolution does your monitor thing the signal is?
The Tandberg says "800x600, 31KHz, 50Hz"
If the problem has shifted, it has done so in a consistent enough way so that all letters look good throughout a MODE 7 screen.
I do notice a slight (almost not noticeable) colour fringing on, for example, the M uprights

hoglet wrote: By the way, did you try building with any of the interesting extensions, like the 65C02 Second Processor, or the SID, or the Music 5000? Lots of fun to be had there....

e.g.

Code: Select all

        generic map (
            IncludeAMXMouse    => false,
            IncludeSID         => true,
            IncludeMusic5000   => true,
            IncludeICEDebugger => false,
            IncludeCoPro6502   => true,
            IncludeCoProSPI    => false,
            UseOrigKeyboard    => false,
            UseT65Core         => false,
            UseAlanDCore       => true
            )
(In the DE1 there's not space for them all at the same time, but the DE2 might be different)

There's also Master 128 mode (SW 9 up I think)

Dave
No, not yet, but I certainly will.
The limitation is just the LEs? If so, the DE2 will have plenty of room to enable everything.
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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 9:57 am

I enabled Music 5000 (and 65C02 CoPro).

Are there any demos readily available for the M5000? Preferably something that can easily be copied onto the SD card.
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 10:29 am

adrm wrote:I enabled Music 5000 (and 65C02 CoPro).

Are there any demos readily available for the M5000? Preferably something that can easily be copied onto the SD card.
There's a Music 5000 disc here:
https://github.com/stardot/b-em/tree/master/discs

You need to use a program called MMB Imager to add the .ssd file into the BEEB.MMB archive on your SD Card:
https://web.archive.org/web/20171002182 ... ndows.html

Music 5000 needs to be run in Master 128 mode (SW9 up).

If you add Music5000.ssd as disc 320, the following should get something playing.

Code: Select all

*INSERT 9
<ctrl break>
*DBOOT 320
*DBOOT 320
Select LOAD PROGRAM, then enter ppach (others to try are pavane and concert)
Select RUN PROGRAM
Dave

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Re: Beeb FPGA

Post by fordp » Mon Dec 04, 2017 11:11 am

The SID is fun too and there are lot of really good demo's on this board.

I had a quick try enabling SID yesterday but I must have done something wrong because it did not work. I had no time to look in to what I did wrong as I was called back to the real world ;)
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 11:30 am

fordp wrote: I had a quick try enabling SID yesterday but I must have done something wrong because it did not work. I had no time to look in to what I did wrong as I was called back to the real world ;)
Are these PJ's Beeb SID disks?

Try them in Beeb mode rather than Master mode.

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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 1:18 pm

I have problems with Music5000.

I inserted the .SSD into drive 2 of BBC.MMB and I can see the files

Executing !BOOT results in the Beeb hard-rebooting itself.

*INSERT 9
etc etc
Gives "Disc not formatted"

Maybe it does not work with the 6502 co-pro enabled at the same time?
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 1:33 pm

adrm wrote: I have problems with Music5000.

I inserted the .SSD into drive 2 of BBC.MMB and I can see the files

Executing !BOOT results in the Beeb hard-rebooting itself.

*INSERT 9
etc etc
Gives "Disc not formatted"

Maybe it does not work with the 6502 co-pro enabled at the same time?
Can you confirm:
- You are using Master 128 mode (SW9 up)
- You have the 65C02 Second Processor disabled (SW6 down)
- After *INSERT 9, you are doing a Control Break

Photos are always helpful!

Dave

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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 1:38 pm

hoglet wrote: Can you confirm:
- You are using Master 128 mode (SW9 up)
- You have the 65C02 Second Processor disabled (SW6 down)
- After *INSERT 9, you are doing a Control Break

Photos are always helpful!

Dave
SW9 is up and the Beeb displays "Acorn MOS \n Master MMFS \n BASIC"

SW6 is DOWN

By Control Break, I assume you need <ctrl> + F12 on the PC keyboard? If yes, this is confirmed.
I.e. Beeb beeps and returns to showing (only) "Acorn MOS \n Master MMFS \n BASIC"
20171204_150252.jpg
Last edited by adrm on Mon Dec 04, 2017 2:12 pm, edited 1 time in total.
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 2:11 pm

adrm wrote: Executing !BOOT results in the Beeb hard-rebooting itself.
How are you executing !BOOT?

Try: *EXEC !BOOT

You need to do this twice:

- The first time you should see some SRLOAD commands flying past, as the AMPLE ROMs are are loaded, then the Beeb will restart

- The second time it should actually start AMPLE.

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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 2:26 pm

hoglet wrote: How are you executing !BOOT?

Try: *EXEC !BOOT

You need to do this twice:

- The first time you should see some SRLOAD commands flying past, as the AMPLE ROMs are are loaded, then the Beeb will restart

- The second time it should actually start AMPLE.
Yes, *EXEC !BOOT is what I tried.
First *EXEC flashes the commands, but I do manage to see a "Disc not formatted" error in there, before the screen clears

A second *EXEC doesn't do anything much (after changing back to DRIVE 2, of course)
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 2:32 pm

adrm wrote: First *EXEC flashes the commands, but I do manage to see a "Disc not formatted" error in there, before the screen clears
The !BOOT file contains the following commands:

Code: Select all

*B.
*SRREAD 880+10 8000 W
IF ?&880=76 THEN *EXEC runner
*SRLOAD R.ample 8000 W Q
*SRLOAD anhf 8000 5 Q
*FX200,3 
CALL!-4 
Can you try them manually, and see where the first error is happening?

Also, can you post the output of *DDRIVE and *ROMS just before you do this?

Do remember the *INSERT 9 followed by Ctrl-F12 after powering up!

Dave

Edit: Regarding *DBOOT 320 failing. You added the Music5000.ssh as disk 2, so you needed to do *DBOOT 2

Also, holding Ctrl and Shift both down should stop printing so you can take a piccie.

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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 2:53 pm

It was the *DBOOT command (Sorry, these commands are unfamiliar to me)

It works great now =D>
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Re: Beeb FPGA

Post by hoglet » Mon Dec 04, 2017 2:57 pm

adrm wrote:It was the *DBOOT command (Sorry, these commands are unfamiliar to me)
This might help:
https://github.com/hoglet67/MMFS/wiki/Command-Reference

Glad it's working now.

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Re: Beeb FPGA

Post by adrm » Mon Dec 04, 2017 3:03 pm

hoglet wrote:
adrm wrote:It was the *DBOOT command (Sorry, these commands are unfamiliar to me)
This might help:
https://github.com/hoglet67/MMFS/wiki/Command-Reference

Glad it's working now.
Thank you.
Saved as PDF for future reference
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Re: Beeb FPGA

Post by adrm » Wed Dec 06, 2017 8:27 am

hoglet wrote:
You need to get yourself a TV with a SCART input. The sRGB mode is indistinguishable from a real Beeb. Do they exist in Norway?

Dave
Just out of curiosity; how does this work?
Last night I was imagining feeding R+G+B+sync to 4 GPIO pins and running this through a cable with a SCART plug in the other end (probably with resistors to bring the signal in line with SCART voltage specifications?)

But looking at the VHDL code I don't see any signs of this having been implemented, so I'm likely wrong.
Still very curious, though.
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Re: Beeb FPGA

Post by fordp » Wed Dec 06, 2017 9:03 am

FordP (Simon Ellwood)
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Re: Beeb FPGA

Post by hoglet » Wed Dec 06, 2017 9:25 am

adrm wrote: Just out of curiosity; how does this work?
Last night I was imagining feeding R+G+B+sync to 4 GPIO pins and running this through a cable with a SCART plug in the other end (probably with resistors to bring the signal in line with SCART voltage specifications?)

But looking at the VHDL code I don't see any signs of this having been implemented, so I'm likely wrong.
Still very curious, though.
It uses the same pins on the VGA connector (R, G, B, HS=composite sync, VS=unused), so a custom (or at least unusual) cable is required. Ideally it should contains 330R resistors inline with the R,G,B signals to drop the TTL level RGB signals to SCART levels.

Here's the bit in the VHDL that switches between VGA and sRGB mode:
https://github.com/hoglet67/BeebFpga/bl ... .vhd#L1647

In sRGB mode, vga0_mode and vga1_mode are both zero.

Dave
Last edited by hoglet on Wed Dec 06, 2017 9:51 am, edited 1 time in total.

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Re: Beeb FPGA

Post by adrm » Wed Dec 06, 2017 9:44 am

Thanks, both.

It's slightly hazy, but I think I generally understand what's going on there.
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Re: Beeb FPGA

Post by hoglet » Wed Dec 06, 2017 9:53 am

adrm wrote: It's slightly hazy, but I think I generally understand what's going on there.
You could easily bring the sRGB signals out elsewhere, e.g. on expansion connection.

There's no reason why VGA and sRGB modes can't both be active at the same time.

Dave

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Re: Beeb FPGA

Post by adrm » Wed Dec 06, 2017 10:37 am

This made me chuckle.
It lists shipping costs as GBP 99.99
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Re: Beeb FPGA

Post by adrm » Wed Dec 20, 2017 10:42 am

Hello, me again.

A quick tip from the FPGA pros, please.

I've been having a hard time trying to figure out how to run simulations with Quartus and ModelSim-Altera. All the examples and tutorials involving setting up testbenches, etc have not worked out for me.

In the end, using a University Program VWF was very simple and worked as described.

However, just looking at inputs and output waveforms involves a certain amount of counting clock pulses to see that everything's working exactly as expected.
Being able to watch the state of selected internal signals, as well, would be great, but I see no way of adding these on the Simulation Waveform Editor.
I only see Edit -> Insert -> Insert Node or Bus, and as far as I can tell internal Signals don't show up here.

Am I overlooking something, or is this not possible?
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Re: Beeb FPGA

Post by hoglet » Sun Jan 14, 2018 7:32 pm

fordp wrote: Any chance of NuLA support on Beeb FPGA?
Coming soon, to a BeebFPGA near you..... :D

At the moment it's parked in a branch:
https://github.com/hoglet67/BeebFpga/commits/videonula

As with Rob's real version, this is essentially a drop-in replacement for the Video ULA component:
https://github.com/hoglet67/BeebFpga/bl ... idproc.vhd

I've tested this on the Altera DE1 and Xilinx Papilio Duo builds, and most things seem to work.

The only missing features are:
- programmable left-hand-side blanking
- Speccy mode

It looks very good with sRGB output, and less good with VGA output (as the scan doubles currently re-samples everything at 16Mhz).

Dave

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Re: Beeb FPGA

Post by hoglet » Sat Jan 20, 2018 6:19 pm

hoglet wrote: The only missing features are:
- programmable left-hand-side blanking
- Speccy mode
I've had a go at the Speccy mode now.

Here's a sample screen I converted coming out of the VideoNuLA in BeebFpga:
IMG_1183s.JPG
Here's a link to the game:
https://spectrumcomputing.co.uk/index.php?cat=96&id=176

The only thing amiss is the palette needs tweaking slightly.

Rob, the only thing I wasn't sure about was the packing of the 4-bit foreground and background colour in the attribute byte.

Which way around are they?

In theory, if I connect a Pi up to BeebFpga, I should be able to run SpectROM when it's released.

Dave

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Re: Beeb FPGA

Post by RobC » Sat Jan 20, 2018 7:02 pm

hoglet wrote:I've had a go at the Speccy mode now.

Here's a sample screen I converted coming out of the VideoNuLA in BeebFpga:
Great stuff =D>
hoglet wrote:Rob, the only thing I wasn't sure about was the packing of the 4-bit foreground and background colour in the attribute byte.
Which way around are they?
At the moment, I've just replicated what the Spectrum does so there's no translation/manipulation of attribute bytes by the emulator. The order is given below with the foreground called "ink" and the background called "paper":

Code: Select all

b7 b6 b5 b4 b3 b2 b1 b0
Fl Br p2 p1 p0 i2 i1 i0
There are actually only 3 colour bits for ink and paper but they also share a bright bit (1=bright, 0=darker) and a flash bit (1=swap paper and ink every 16 frames, 0=maintain original colours). Unlike on the Beeb, for ink and paper, b0=blue, b1=red and b2=green. To produce the flashing colours (as you might expect!), I just take the the flash bit/b0 of the Beeb ULA's control register, AND it with the attribute flash bit and then swap the output colours if the result is true. The emulator manipulates the ULA flash bit at the required rate.
hoglet wrote:In theory, if I connect a Pi up to BeebFpga, I should be able to run SpectROM when it's released.
Excellent. I'm hoping to make enough progress to release something next week.
Last edited by RobC on Sat Jan 20, 2018 8:05 pm, edited 1 time in total.

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Re: Beeb FPGA

Post by hoglet » Sat Jan 20, 2018 7:34 pm

RobC wrote: At the moment, I've just replicated what the Spectrum does so there's no translation/manipulation of attribute bytes by the emulator.
Ahh, I've misunderstood then.

I've a bit more work to do....

Dave

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Re: Beeb FPGA -> My new (used) DE1

Post by adrm » Wed Jan 24, 2018 6:19 pm

So, I found a cheap-ish DE1 and figured "why not", as a lot of the development here is for that board.

I have now fired it up and tried to determine if it works as it should.

Initial observations:

1)
Connecting a USB keyboard via a PS/2 adapter does not seem to work (as per Hoglet's worry earlier in this thread), unlike the DE2 where it works fine.
For now I'm assuming this is a limitation of the DE1.

2)
Connecting the Tandberg ErgoScan LCD screen I have mentioned before does not produce a picture at all, after loading up the Beeb DE1 core (downloaded directly from GitHub).
I have tried loading an Apple II core that partially works and this produces a picture on the screen.
I have tried playing with SW7 and SW8. SW7 up (31.5KHz) gives the "Out of timing" error on the screen, while SW7 down (15.875KHz) gives a black screen. SW8 position makes no difference.
Since I can get this screen to work with the DE2, I guess there is a chance of getting it to work with the DE1? Hoglet mentioned something about the difference in RGB/VGA outputs for these boards.

3)
Another question for DE1 owners:
The leftmost digit of the LED display on this board is noticeably dimmer than the other 3. Is this normal?


PS!
I have obtained a USB <-> RS232 cable I will try to use for debugging, but for now I haven't been bale to make it work with PUTTY.
Not sure if there is a problem with the cable or if it's on me (probably the latter), but I'll fiddle with it.


Edit: Got the debugger working too.
Nice!
Last edited by adrm on Wed Jan 24, 2018 9:37 pm, edited 2 times in total.
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Re: Beeb FPGA

Post by adrm » Wed Jan 24, 2018 7:17 pm

Ok, solved problem 2.
(Using out of date software to load the FLASH)

I do notice that MODE 7 text is no better than on the DE2.
I thought the DE1's "simpler" circuitry would give a better result, but maybe I misunderstood?

Edit:
Problem 1 is solved, as well
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Re: Beeb FPGA -> My new (used) DE1

Post by hoglet » Wed Jan 24, 2018 7:33 pm

adrm wrote: Connecting a USB keyboard via a PS/2 adapter does not seem to work (as per Hoglet's worry earlier in this thread), unlike the DE2 where it works fine.
For now I'm assuming this is a limitation of the DE1.
More likely the USB keyboard doesn't support PS/2 mode, or the PS/2 adapter is a mouse adapter, not a keyboard adapter.

Dave

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