Beeb FPGA

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adrm
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Re: Beeb FPGA

Post by adrm » Fri Dec 01, 2017 11:43 pm

> Have you changed the pin assignment to match the DE2? (In the .QSF file)? This is the most likely source of errors.

Yes, I even loaded it again and recompiled.

> Try all four combinations of SW7 and SW8.

Setting SW7: 15.875KHz gives "Out of Timing" no matter what SW8 is

Setting SW8 to RGBtoVGA + SW7 to 31.5KHz: "No Signal"
Setting SW8 to Mist + SW7 to 31.5KHz: Just a black screen
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Re: Beeb FPGA

Post by adrm » Fri Dec 01, 2017 11:48 pm

Pressing <ctrl>-G or Reset (KEY[0]) gives out the expected Beeb sounds from the line out connector.
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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 12:09 am

I haven't been able to determine if you use the 27MHz clock.

If so, maybe this line from v1.3 of the DE2 User Manual might be a clue?
"Important: To use the 27 MHz clock, the TD_RESET pin (PIN_C4) must be asserted to a high logic level. "


Edit: Had to try it. Setting TD_RESET high, i.e. "TD_RESET <= '1';", didn't change anything.
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hoglet
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 7:42 am

adrm wrote:Pressing <ctrl>-G or Reset (KEY[0]) gives out the expected Beeb sounds from the line out connector.
This is a good sign!

Is that using a different keyboard, or using the USB-to-PS/2 adapter?
adrm wrote: I haven't been able to determine if you use the 27MHz clock.
It's used for one of the scan doublers (the RGB2VGA one).

It does look like this might be a video-only issue.

Can you try changing to a different mode, e.g. mode 6:
- either by blind typing in MODE 6
- or by setting SW2..SW0 appropriately and resetting the system

(One of the scan doublers struggles with Mode 7, I forget which)

Another possibility is that your VGA monitor isn't compatible with 50Hz VGA (many aren't). What model is it?

Do you have a TV with a SCART input?

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 9:02 am

hoglet wrote:
Is that using a different keyboard, or using the USB-to-PS/2 adapter?
This is with the USB keyboard w. the converter.

hoglet wrote: Another possibility is that your VGA monitor isn't compatible with 50Hz VGA (many aren't). What model is it?

Do you have a TV with a SCART input?

Dave
No TV with SCART, I'm afraid. My preferred unit for retro computers is an old Tandberg ErgoScan MT17 because it has a 3:4-ish aspect ratio (and takes up little space on my desk)

But now I have connected up my older Eizo FlexScan S2401W, which also has VGA in.

The Eizo does not complain about timing at all.
However ~35KHz gives no video signal (same as the Tandberg)
In 15.8KHz mode the Eizo displays "0" for both H and V sync

I can connect my scope to the VGA port and report back what I find

PS! The VGA output from the board is working as intended. I.e it shows the expected Altera screen in the Tandberg when powering it on.

PPS!
I have found the following data for the Eizo:
Scanning Frequency (H, V):
Analog: 24 - 94 KHz, 49 - 86 Hz
Digital: 31 - 76 KHz, 59 - 61 Hz (VGA Text: 69 - 71 Hz)
Last edited by adrm on Sat Dec 02, 2017 11:16 am, edited 1 time in total.
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Re: Beeb FPGA - Scoping the VGA output from the DE2

Post by adrm » Sat Dec 02, 2017 9:41 am

(I have never tried looking at VGA signal before, so I'm not 100% sure what I'm doing.)

The H and V Sync signal seem to be working as expected, i.e the expected frequencies are output.

When looking at the R / G / B pins, however, things get a little murkier.
I would have expected to see a "blip", i.e. 0.7-ish Volts, more than every 50Hz to reflect the BBC logo in the upper left corner.

I can only see a constant 0.3 mV output from these pins. (Plus a little noise)
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 12:21 pm

OK, so it seems from the specifications that your monitor should work with a 50Hz/31.25KHz VGA signal.

It would really help if you could make your code available somehow. A fork on github would be ideal, but failing that just Zip everything up and upload it to a free account on dropbox.

Did you build with the 6502 debugger? i.e. you still have this setting in src/altera/bbc_micro_de1.vhd

Code: Select all

            IncludeICEDebugger => true
If so, it would be useful to try to get a serial cable connected. Then you can see what code the 6502 is executing, and read/write memory etc.

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 12:50 pm

Unfortunately, none of the computers I have lying around have a serial port.
That is, there is a small chance that a laptop I have stored away has one. I'll check that later today.


The code is 99,999% similar to the original. I have ZIPed up the while structure here.
Link: https://www.dropbox.com/sh/1odonphercjc ... Bauca?dl=0
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 1:02 pm

I've got my DE1 setup on the desk next to me now, so I should be able to check a few more things with you.

I will check I can rebuild everything from source, but I need to re-install Quartus (as I have a new dev machine) so that might take an hour. It is possible a bug has crept in, as I don't test the Altera target very often.

I'm using VGA output, so I have SW7 up and all other switches down.

When the system power up I would expect to see:
- 8888 on the hex display - this is showing the 6502's address bus, which is changing too fast to see
- Just LED R0 lit up; this is the Caps Lock LED

Pressing Caps Lock on the keyboard should toggle LED R0.

Holding down F12 (Break) on the keyboard should show FFFC on the Hex Display (this is the 6502's reset vector), and both LED R0 and LED R1 should be on when F12 is depressed.

Can you confirm you are seeing that?

I then have a few more further tests you can try.

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 1:13 pm

hoglet wrote:I've got my DE1 setup on the desk next to me now, so I should be able to check a few more things with you.
I'm using VGA output, so I have SW7 up and all other switches down.

When the system power up I would expect to see:
- 8888 on the hex display - this is showing the 6502's address bus, which is changing too fast to see
- Just LED R0 lit up; this is the Caps Lock LED

Pressing Caps Lock on the keyboard should toggle LED R0.

Holding down F12 (Break) on the keyboard should show FFFC on the Hex Display (this is the 6502's reset vector), and both LED R0 and LED R1 should be on when F12 is depressed.

Can you confirm you are seeing that?

I then have a few more further tests you can try.

Dave
I can confirm everything you say, except that LEDR(13) is also ON
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 1:32 pm

adrm wrote: I can confirm everything you say, except that LEDR(13) is also ON
OK, I'm not sure about LED R13 as the DE1 board only had LED's R0-R9 and G0-G7. Let's park that one for now.

I think I've spotted an issue with your changes, and it comes down to the missing 24MHz clock.

On the DE1 BeebFPGA, the 24MHz clock is used for two things:
1. To generate the 32MHz Beeb system clock (using a PLL)
2. To clock the SAA5050 teletext chip used for Mode 7

You seem to have sorted (1), but not (2).

Which means that Mode 7 will not give any output.

Try putting SW0 in the up position, then pres Ctrl-F12 (F12 emulates the Beeb's BREAK key). The system should restart in Mode 6, and you might just see something on the screen.

Also make sure SW7 is up and SW8 is down, which selects VGA mode with the MIST scan doubler (the one that doesn't use 27MHz).

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 1:49 pm

hoglet wrote:
adrm wrote:
Try putting SW0 in the up position, then pres Ctrl-F12 (F12 emulates the Beeb's BREAK key). The system should restart in Mode 6, and you might just see something on the screen.

Also make sure SW7 is up and SW8 is down, which selects VGA mode with the MIST scan doubler (the one that doesn't use 27MHz).

Dave
This configuration just gives a black / blank screen on both monitors.

(As opposed to SW7 down which makes them complain about timing)
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 2:17 pm

adrm wrote:
hoglet wrote:
adrm wrote:
Try putting SW0 in the up position, then pres Ctrl-F12 (F12 emulates the Beeb's BREAK key). The system should restart in Mode 6, and you might just see something on the screen.

Also make sure SW7 is up and SW8 is down, which selects VGA mode with the MIST scan doubler (the one that doesn't use 27MHz).

Dave
This configuration just gives a black / blank screen on both monitors.

(As opposed to SW7 down which makes them complain about timing)
OK, so another possible issue is the VGA output on the DE2 uses 10-bit colours, and the DE1 uses just 4-bit colours.

I think by default you will be driving the just the least significant 4 bits, which might explain the black screen.

You need to change:

Code: Select all

    -- VGA
    VGA_R       :   out std_logic_vector(3 downto 0);
    VGA_G       :   out std_logic_vector(3 downto 0);
    VGA_B       :   out std_logic_vector(3 downto 0);
to

Code: Select all

    -- VGA
    VGA_R       :   out std_logic_vector(9 downto 0);
    VGA_G       :   out std_logic_vector(9 downto 0);
    VGA_B       :   out std_logic_vector(9 downto 0);
And then further down change:

Code: Select all

            video_red      => VGA_R,
            video_green    => VGA_G,
            video_blue     => VGA_B,
to

Code: Select all

            video_red      => VGA_R(9 downto 6),
            video_green    => VGA_G(9 downto 6),
            video_blue     => VGA_B(9 downto 6),
Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 2:45 pm

Unfortunately still no luck.

The change I believe I'm seeing is that earlier the screen was showing nothing + the backlight.
Now it seems to be showing true black.

If that makes any sense?
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 2:47 pm

adrm wrote:Unfortunately still no luck.

The change I believe I'm seeing is that earlier the screen was showing nothing + the backlight.
Now it seems to be showing true black.

If that makes any sense?
Yes, it does.

We'll get there in the end!

I've just spotted the DE2 VGA interface has two additional signal, VGA_BLANK and VGA_SYNC. The DE1 has neither of these.

Looking at the datasheet for the ADV7123 Video DAC that is used:
https://people.ece.cornell.edu/land/cou ... DV7123.pdf

If VGA_BLANK is low, the display will be blanked (i.e. R, G, B all forced to 0).

So you definitely need to add VGA_BLANK to the design, and drive it to a '1'.

There is also VGA_SYNC, which I'm just reading about now. Try driving that to '1' as well.

If that doesn't work, it may be VGA_BLANK and VGA_SYNC need to be driven correctly with suitable blank and sync, which would be a pain.

Dave
Last edited by hoglet on Sat Dec 02, 2017 3:13 pm, edited 1 time in total.

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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 3:13 pm

Gosh, this is turning out to be quite non-trivial.

As well as VGA_BLANK, and VGA_SYNC, the ADV7123 needs a pixel clock: VGA_CLK.

I suspect without this you will get nothing at all.

So you also need to feed Clock_32 out as VGA_CLK.

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 3:28 pm

I have driven VGA_BLANK to HIGH, with or without VGA_SYNC being forced HIGH at the same time.
I did this in "bbc_micro_de1", not in "rgb2vga_scandoubler". I assume that's ok?

Anyway, SW8 down still gives no signal, just the backlight.
SW8 in up position gives a BLACK background.

Summary:
Unless I need to drive BLANK / SYNC high in another part of the code, nothing changed

Edit: I'll try your last suggestion a little later and report back.
Thank you for your effort, so far :)
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 3:46 pm

adrm wrote: I did this in "bbc_micro_de1", not in "rgb2vga_scandoubler". I assume that's ok?
Yes, that's the best place.

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 4:43 pm

hoglet wrote:Gosh, this is turning out to be quite non-trivial.

As well as VGA_BLANK, and VGA_SYNC, the ADV7123 needs a pixel clock: VGA_CLK.

I suspect without this you will get nothing at all.

So you also need to feed Clock_32 out as VGA_CLK.

Dave
Yep. That did the trick. We now have VGA working .... -ish

The text is blocky (I seem to recall text smoothing being discussed in the thread), and I only get what looks like MODE 6, no matter what position SW0-3 are in.
Typing, e.g. "*MODE 0" results in "Card?", a message I don't remember from way back then (although I vaguely recall seeing in mentioned elsewhere)

But hey, real progress. Fantastic! :)

Edit:
Flipping SW[0..2] and then pressing KEY[0] will change modes, and MODE 7 does not work (as predicted)
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 5:01 pm

Great progress!
adrm wrote: The text is blocky (I seem to recall text smoothing being discussed in the thread), and I only get what looks like MODE 6, no matter what position SW0-3 are in.
Can you post a photo?

(Leave SW 3 down, it's the file system auto-boot selector, which needs to be off)
adrm wrote: Typing, e.g. "*MODE 0" results in "Card?", a message I don't remember from way back then (although I vaguely recall seeing in mentioned elsewhere)
Card? is the error you get when you try to access the SD Card file system (MMFS) and don't have a card plugged in.

Do you get to the BBC Basic > prompt? MODE 0 shouldn't actually be trying to access the file system. So that's a bit of a mystery. Anyway, another photo of this might help.

You need to format a SD Card (FAT32), and then unzip this BEEB.MMB file onto it:
https://github.com/hoglet67/Ice40Beeb/r ... EB.MMB.zip

Then you should be able to *CAT and see some files.

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 5:14 pm

hoglet wrote:Great progress!
adrm wrote: The text is blocky (I seem to recall text smoothing being discussed in the thread), and I only get what looks like MODE 6, no matter what position SW0-3 are in.
Can you post a photo?

(Leave SW 3 down, it's the file system auto-boot selector, which needs to be off)
adrm wrote: Typing, e.g. "*MODE 0" results in "Card?", a message I don't remember from way back then (although I vaguely recall seeing in mentioned elsewhere)
Card? is the error you get when you try to access the SD Card file system (MMFS) and don't have a card plugged in.

Do you get to the BBC Basic > prompt? MODE 0 shouldn't actually be trying to access the file system. So that's a bit of a mystery. Anyway, another photo of this might help.

You need to format a SD Card (FAT32), and then unzip this BEEB.MMB file onto it:
https://github.com/hoglet67/Ice40Beeb/r ... EB.MMB.zip

Then you should be able to *CAT and see some files.

Dave
Photos will be forthcoming by tomorrow, as my daughter needs a study buddy for her veterinary exams tonight.

SW[0..3]: I meant 0..2.
Numbers above ... 1 ... are hard :shock:

I'll format an SD card tonight, but I'm really puzzled as to why the "*MODE" command didn't work. I'll experiment further.

An Hello World program executed fine, btw
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Re: Beeb FPGA

Post by BigEd » Sat Dec 02, 2017 5:16 pm

I think you said you typed "*MODE" - but it's not a star command! At the Basic ">" prompt you just type "MODE"

Or, as Dave has shown me, you can use control-V and then type a digit, and that works too to change the mode.

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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 5:32 pm

#-o I missed the *

Yes, definitely just MODE, not *MODE

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 6:00 pm

Ahhh!
It's been too long
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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 7:51 pm

Question about Teletext mode

I find this in SAA5050.VHD:
entity saa5050 is
port (
CLOCK : in std_logic;
-- 6 MHz dot clock enable
CLKEN : in std_logic;
-- Async reset
nRESET : in std_logic;
-- Character data input (in the bus clock domain)
DI_CLOCK : in std_logic;

And this in BBC_MICRO_CORE.VHD
teletext : entity work.saa5050 port map (
clock_24, -- This runs at 12 MHz, which we can't derive from the 32 MHz clock
ttxt_clken,
hard_reset_n,
clock_32, -- Data input is synchronised from the bus clock domain


Where does the 27MHz clock enter into this? I get the impression that only the 32 and 24 MHz clocks feed into it?
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 7:56 pm

adrm wrote: Where does the 27MHz clock enter into this?
It doesn't, it's only used in the alternative scan doubler.
adrm wrote: I get the impression that only the 32 and 24 MHz clocks feed into it?
Correct.

The issue is you don't have a 24MHz clock going in.

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 8:06 pm

Thanks.
Hopefully I can fix that in short order.

PS!
I tried switching to the alt scan doubler now that I have a 27MHz clock going. I do get text on the screen, but it's highly unstable.
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Re: Beeb FPGA

Post by hoglet » Sat Dec 02, 2017 8:12 pm

adrm wrote: I tried switching to the alt scan doubler now that I have a 27MHz clock going. I do get text on the screen, but it's highly unstable.
Agreed, it's like that for me - it depends a lot on the monitor. I probably should take it out.

Dave

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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 9:22 pm

I'm creating another PLL for a 24MHz clock, but now my lack of experience has me stymied.

The way I understand it, each PLL uses an input clock and generates one (or more) output clock based on this.
I was assuming that this would generally be the 50MHz clock on these boards.
Furthermore, I find that the identifier "CLOCK_50" is defined in the .QSF file and this again refers to a specific pin on the FPGA that the HW clock generator feeds into.
I then expected CLOCK_50 to be what would be used for all PLLs, but this is apparently not the case, as the compiler throws an error about not using the same input clock for multiple PLLs.

So, what is the approved way to resolve this?
E.g. feed CLOCK_50 into multiple SIGNALS and then feed these into the PLLs?
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Re: Beeb FPGA

Post by adrm » Sat Dec 02, 2017 9:30 pm

hoglet wrote:Great progress!
adrm wrote: The text is blocky (I seem to recall text smoothing being discussed in the thread), and I only get what looks like MODE 6, no matter what position SW0-3 are in.
Can you post a photo?

Dave
Picture of MODE 6 text:
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