Beeb FPGA

discuss both original and modern hardware for the bbc micro/electron
User avatar
oss003
Posts: 3364
Joined: Tue Jul 14, 2009 12:57 pm
Location: Netherlands
Contact:

Re: Beeb FPGA

Post by oss003 » Wed Nov 04, 2015 8:29 pm

+1 =D> =D> =D> =D>

Greetings
Kees

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 04, 2015 9:01 pm

sPhilMainwaring wrote: Edit: Also when you mention the 6522 do you just mean the system via or do you also reproduce the user via / user port and are the I/O pins available for software that reads and writes to the user port (Does this include the printer port too?)
The user VIA is included. Port B (the user port) is connected to the SD Card (i.e. as per Beeb MMC). Port A (the printer port) is not connected to anything yet, but could easily be routed to one of the FPGA board connectors. It would be 3.3V levels though, so not directly useful without level shifters (i.e. a bit of external circuitry).
sPhilMainwaring wrote: Edit 2: Also, also this got me thinking about the PS/2 keyboard ... does this just go into the FPGA alchemy and get decoded or does it somehow get mapped to an array of read write pins that are accessible on the board ...
That's how it currently works.
sPhilMainwaring wrote: what I mean here is could we buy an old beeb shell with a beeb keyboard and be able to simply connect the keyboard/boot options via a ribbon cable to your FPGA thingymajig ... how does this black magic work!
That would be possible, but again you would need 3V3 to 5V level shifters in between.
sPhilMainwaring wrote: Edit 1 (or edit 3): The dual joystick port adaptor looks cool ... I was thinking more along the lines of how easy is the beeb A/D circuitry to copy / replicate / modernise and extract from a main beeb circuit diagram
You just need a way to connect an A/D converter into the Papilio Duo board, i.e. something like this:
http://papilio.cc/index.php?n=Papilio.AnalogGroveWing
which uses an SPI interface on the digital side.
sPhilMainwaring wrote: Sorry I don't know much about the internals of the FPGA stuff you use ... I guess my low level view of it is doesn't everything ultimately connect to logic and ICs connected to address, data and control lines and are the internal FPGA representations of these "extendible" outside the FPGA box? Maybe these are silly questions or maybe they might change / help implementation?
Yes, internally these is an address/data/control bus, but the timing of this is a bit different from a real Beeb (e.g. the master clock is actually 32 MHz) and all the signals are synchronous. Over time I'd like to make this more Beeb like, which would make interfacing to legacy peripherals (e.g. over a 1MHz bus) more straight forward. At the moment, none of these buses are externalized to headers.
sPhilMainwaring wrote: I remember we were talking about this at ABUG in August (especially the "near 64K limits") but I didn't really understand parts ... just that it would be _cool_
If there is an external SRAM (as on the Papilio Duo), the 64K limit (of internal FPGA RAM with the LX9) is less of a problem.
sPhilMainwaring wrote: Needy aren't I :)
:lol: :lol: :lol:

Dave
Last edited by hoglet on Wed Nov 04, 2015 9:32 pm, edited 1 time in total.

User avatar
1024MAK
Posts: 10292
Joined: Mon Apr 18, 2011 5:46 pm
Location: Looking forward to summer in Somerset, UK...
Contact:

Re: Beeb FPGA

Post by 1024MAK » Wed Nov 04, 2015 9:31 pm

+2 =D> =D> =D> =D>


Excellent work, as always from Dave :D

Mark

User avatar
daveejhitchins
Posts: 5912
Joined: Wed Jun 13, 2012 6:23 pm
Location: Newton Aycliffe, County Durham
Contact:

Re: Beeb FPGA

Post by daveejhitchins » Wed Nov 04, 2015 10:15 pm

+3 & +4 (my alter-ego) =D>

Dave H =D>

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 04, 2015 10:31 pm

Now stop this guys, you are making me blush :oops: :oops: :oops:

:lol:

User avatar
sPhilMainwaring
Posts: 300
Joined: Tue Jan 15, 2013 7:57 pm
Location: Mid Wales
Contact:

Re: Beeb FPGA

Post by sPhilMainwaring » Thu Nov 05, 2015 11:05 am

Thanks for the explanations Dave :)

Do I remember this or have I imagined it? An FPGA SID card for the FPGA Atom? Would it be possible for an FPGA SID for the FPGA Beeb?

I was thinking if an FPGA can mimic a 32MHz 6502 could it not also mimic 2 x 16 MHz 6502s? :)

Oh wait a minute no the SID was executed by the main 6502 on an interrupt hey!

So I guess I'm asking the first question can the FPGA mimic SID _and_ is there room in the Beeb and Atom FPGAs?

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Thu Nov 05, 2015 11:54 am

sPhilMainwaring wrote: Do I remember this or have I imagined it? An FPGA SID card for the FPGA Atom? Would it be possible for an FPGA SID for the FPGA Beeb?
AtomFPGA can already be compiled to include a SID. As do the GODIL FPGA modules in all of Roland's New Atoms.

Adding this internally into BeebFPGA should be possible, as would adding a Music 5000.
sPhilMainwaring wrote: I was thinking if an FPGA can mimic a 32MHz 6502 could it not also mimic 2 x 16 MHz 6502s? :)

Oh wait a minute no the SID was executed by the main 6502 on an interrupt hey!

So I guess I'm asking the first question can the FPGA mimic SID _and_ is there room in the Beeb and Atom FPGAs?
Yes and yes.

Dave

User avatar
sPhilMainwaring
Posts: 300
Joined: Tue Jan 15, 2013 7:57 pm
Location: Mid Wales
Contact:

Re: Beeb FPGA

Post by sPhilMainwaring » Thu Nov 05, 2015 12:32 pm

Great !

We just need to find someone with a decent 3D printer who can "print" Atom Cases :D

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Thu Nov 05, 2015 6:24 pm

So, today I thought I would do something easy, and add hold-graphics support to the SAA5050.

There's a great thread here with an excellent teletext engineering test page:
http://www.stardot.org.uk/forums/viewto ... 6&p=109200

So, this morning here's what it looked like on BeebFPGA:
IMG_0126.JPG
Turns out there was much more than just graphics-hold that wasn't quite correct.

What I hadn't appreciated was that certain control codes are "Set-At" and take effect immediately, and other control codes are "Set-After" and take effect at the next character. It's all pretty hairy stuff, that's explained on page 76 of the ETSI Spec:
http://www.etsi.org/deliver/etsi_i_ets/ ... 06e01p.pdf
(thanks to Dreamland Fantasy for posting this)

Anyway, many hours later, it now looks correct:
IMG_0127.JPG
Time for a glass of wine!

Question - are there any archives of BBC Teletext Pages in .SSD format anywhere that I could use to do more testing with. I seem to remember some people (BeebMaster?) collecting a load before CeeFax was shut down.

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Thu Nov 05, 2015 6:40 pm

hoglet wrote:Question - are there any archives of BBC Teletext Pages in .SSD format anywhere that I could use to do more testing with. I seem to remember some people (BeebMaster?) collecting a load before CeeFax was shut down.
I found PitfallJones's BeebFax collection, so I'll test with those as a start.

Any more?

Dave

User avatar
sydney
Posts: 2721
Joined: Wed May 18, 2005 10:09 am
Location: Newcastle upon Tyne
Contact:

Re: Beeb FPGA

Post by sydney » Sat Nov 07, 2015 9:25 am

First off great work =D> . I love reading what you get up to, every time I read one of your post's I start googling VHDL and looking at ebay!
Second. How hard would it be to move the output from a VGA connector to something that would work with an LCD panel in a laptop? I'm wondering if it would be possible to buy a dead laptop on ebay, remove the motherboard and connect the fpga beeb to the keyboard and screen. If thats a no go there are 14" lcd screens with vga inputs available on ebay for around £60-£70 and thats price I'd be happy to pay for a portable beeb!

User avatar
flynnjs
Posts: 831
Joined: Tue Jul 06, 2010 10:33 pm
Contact:

Re: Beeb FPGA

Post by flynnjs » Sat Nov 07, 2015 12:11 pm

LVDS drive is not too bad to implement on an FPGA but scoop up quick as most new laptop LCDs are eDP rather than LVDS.
I've been thinking exactly the same thing since I saw Mike Stirling's code but have been too busy with other projects.
Now the next copro pcbs are en-route I feel like tinkering with this until they arrive.

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Sat Nov 07, 2015 6:38 pm

Hi Jason,
flynnjs wrote:LVDS drive is not too bad to implement on an FPGA but scoop up quick as most new laptop LCDs are eDP rather than LVDS.
I've been thinking exactly the same thing since I saw Mike Stirling's code but have been too busy with other projects.
Now the next copro pcbs are en-route I feel like tinkering with this until they arrive.
Does "this" mean scan doublers or Beeb FPGA? What you planning to do?

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Sat Nov 07, 2015 6:46 pm

Something cool happened to Beeb FPGA this afternoon.....It evolved into a Master 128 :shock:
IMG_0135.JPG
At the moment the RTC/CMOS settings are hard coded to sensible values:
IMG_0136.JPG
These are writeable (i.e. *CONFIGURE can be used), but not yet persisted back to FLASH memory (this could be done if needed I think).

I think all the shadow stuff is working.

The changes were not too bad:
https://github.com/hoglet67/BeebFpga/co ... 30d4ae1fa4

I've now got a VHDL "generic" (ModeM128) which selects at compile time whether this is a Model B or Master build. This also needs a 65C02 processor (I think....). And obviously different ROMs.

I have a couple of questions:
- Does anyone have a BEEB.MMB file with some Master-only stuff on that I can test with?
- Is there a version of SUPERMMC or SMARTSPI that uses the private file system workspace, so page stays at &E00?

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Sat Nov 07, 2015 7:03 pm

And another question.

Reading this page, I was expecting to have to make some changes to the keyboard.
http://www.cloud9.co.uk/james/BBCMicro/ ... aster.html
During idle (free run) mode depression of any keys other than SHIFT/CTRL
will cause an IRQ to be generated via the system 6522. The keyboard column
lines C0-C12 are continually scanned by incrementing a counter, decoding its
outputs and pulling low a column line. Any key depressed will cause an
interrupt to be generated. A keyboard enable signal (KBEN) is generated to
stop free running mode at which point the counter contents are loaded by CPU
operation to determine on which column the key was pressed. The rows are
then individually selected to determine which key was pressed.

NB. This appears to contrast to the BBC B way of doing things.
But it seems to work fine.

I guess I don't understand the difference being hinted at, and whether this is hardware or software?

Are there keyboard *hardware* differences I should be aware of between the Model B and Master, other than the additional keys.

Dave

User avatar
flynnjs
Posts: 831
Joined: Tue Jul 06, 2010 10:33 pm
Contact:

Re: Beeb FPGA

Post by flynnjs » Sat Nov 07, 2015 8:03 pm

hoglet wrote: What you planning to do?
I think I'm going to build an LVDS driver which will have various bits in it
to adapt Beeb resolutions to LCD panels. This might not be the same as
any type of scan doubler needed for VGA. I also don't have all the LVDS
display wired up yet so this isn't going to be a fast development.

duikkie
Posts: 2987
Joined: Fri Feb 07, 2014 3:28 pm
Contact:

Re: Beeb FPGA

Post by duikkie » Sun Nov 08, 2015 2:29 pm

- Is there a version of SUPERMMC or SMARTSPI that uses the private file system workspace, so page stays at &E00?


you can make a version that has &a00 as value space . change dvars%

because smart-spi is dfs 0.9 it sets the page to &1900. look in file "make" to change that.

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Sun Nov 08, 2015 3:06 pm

duikkie wrote:- Is there a version of SUPERMMC or SMARTSPI that uses the private file system workspace, so page stays at &E00?

you can make a version that has &a00 as value space . change dvars%

because smart-spi is dfs 0.9 it sets the page to &1900. look in file "make" to change that.
By private file system workspace, I meant the 8K shadow RAM that exists on the master from C000-DFFF.

This is what the Master DFS 2.24 use as workspace instead of main memory, allowing page to stay at E00.

I guess because SUPERMMC/SMARTSPI is based on DFS 0.9 then this isn't used.

Dave

duikkie
Posts: 2987
Joined: Fri Feb 07, 2014 3:28 pm
Contact:

Re: Beeb FPGA

Post by duikkie » Sun Nov 08, 2015 3:32 pm

on a normal beeb &c000.. &dfff is OS rom area. no shadow , therefor tape machine is at &e00.. disc machine are at &1900 .

mmc roms use &e00.&f00 for in and output data. therefor all programs have a downloader if they are from tape &e00.

further is my smart spi full about 3fff bytes long , so no space left there
hoglet wrote:
duikkie wrote:- Is there a version of SUPERMMC or SMARTSPI that uses the private file system workspace, so page stays at &E00?

you can make a version that has &a00 as value space . change dvars%

because smart-spi is dfs 0.9 it sets the page to &1900. look in file "make" to change that.
By private file system workspace, I meant the 8K shadow RAM that exists on the master from C000-DFFF.

This is what the Master DFS 2.24 use as workspace instead of main memory, allowing page to stay at E00.

I guess because SUPERMMC/SMARTSPI is based on DFS 0.9 then this isn't used.

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 11, 2015 3:04 pm

Short update for today....

I'm now using MMFS as the default filing system in the Master, so that PAGE can stay at &E00. See the other thread for the fixes to support SDHC cards, and also the FSCV calls to make *EX and *INFO work.

I spent yesterday evening adding digital joystick support via an internal analogue port. I've wrote a simple VHDL implementation of the uPD7002. It's got an internal counter, so the timing of the conversion interrupts should be correct, even if there is no actual conversion to be done.

This is all working nicely, and I can now fire up the master version of Elite using MMFS and play it with an Atari style joystick. Shame I'm rubbish at Elite. :lol:

It took me a while to get the joysticks debugged. At the register level it all seemed to be working, but ADVAL was returning some very strange results. ICE-T65 to the rescue - it's really useful having this integrated as well. I was able to single step through the conversion code in the MOS, and it became apparent that the reason it wasn't working correctly was the D flag somehow getting set in the interrupt handler, so it was using decimal mode arithmetic rather than normal arithmetic. :shock: This turned out to be a bug in the 65C02 core that I'm using, which has now been fixed. I'm pretty amazed this wasn't messing other things up.

I don't know what's next yet, but I'm sure I'll find something to keep me entertained :D

Dave

User avatar
fordp
Posts: 1098
Joined: Sun Feb 12, 2012 9:08 pm
Location: Peterborough, England
Contact:

Re: Beeb FPGA

Post by fordp » Wed Nov 11, 2015 4:28 pm

Well done Dave this is awesome.

The high page setting when using the DFS is a long standing problem and this new MMFS sounds great. I will have to see if I can use it on my real Master.

I have one question.

Will your HDL still run on the DE1 that it came from in the first place as I do not have your FPGA board of choice, but I have DE1's galore.

I ordered a MIST + MIDI from Poland at lunch time as I am desperate to try every BBC core going ;)

Keep up the great work.

I hope I can help at least by adding MIDI features (I have a real MIDI Interface for my real Master and lots of 80's MIDI Synths to play with).

All the best.

FordP
FordP (Simon Ellwood)
Time is an illusion. Lunchtime, doubly so!

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 11, 2015 4:42 pm

fordp wrote: Will your HDL still run on the DE1 that it came from in the first place as I do not have your FPGA board of choice, but I have DE1's galore.
I would need "porting" back again, as Altera and Xilinx do certain things differently (e.g. the clock PLLs).

Is your offer of a DE1 still on the table?

I'd be up for having a go at porting this back to the DE1 if it means more (i.e. >1) people using this.
fordp wrote: I hope I can help at least by adding MIDI features (I have a real MIDI Interface for my real Master and lots of 80's MIDI Synths to play with).
What's the MIDI Physical Layer look like?

The Papilio needs a special wing for this:
http://papilio.cc/index.php?n=Papilio.MIDIAudioWing

Looks like it just contains an Opto Coupler.

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 11, 2015 4:52 pm

Here's another Midi Wing:
http://retrocade.gadgetfactory.net/inde ... gaWingMIDI

Looks like the opto isolation is on the input, so doing midi output doesn't require any special hardware at all.

I did an FPGA Implementation of the Music 5000 last year, and it's pretty small so it should fit in as well:
viewtopic.php?t=8901

Dave

JonC
Posts: 732
Joined: Wed May 14, 2014 10:19 pm
Location: Wakefield
Contact:

Re: Beeb FPGA

Post by JonC » Wed Nov 11, 2015 5:08 pm

hoglet wrote: I don't know what's next yet, but I'm sure I'll find something to keep me entertained :D

Dave
Econet/Ethernet solution using an RJ45 port on a wing? :)

This would be great for those who want to build an Econet/L3 Fileserver/Network Bridge etc, but are short on space. :mrgreen:
The wing could also use this econet clock: http://www.stardot.org.uk/forums/viewto ... f=3&t=8000
Jon
Image

User avatar
fordp
Posts: 1098
Joined: Sun Feb 12, 2012 9:08 pm
Location: Peterborough, England
Contact:

Re: Beeb FPGA

Post by fordp » Wed Nov 11, 2015 6:23 pm

Hi Dave,
I will send you a DE1 if you send me your address.

MIDI hardware is pretty simple to implement. See the Mist MIDI board for what is needed.

My interface is just a 6850 on the user port so very simple to pop in an FPGA.

Happy days :D

FordP
Last edited by fordp on Thu Mar 07, 2019 6:47 pm, edited 1 time in total.
FordP (Simon Ellwood)
Time is an illusion. Lunchtime, doubly so!

User avatar
fordp
Posts: 1098
Joined: Sun Feb 12, 2012 9:08 pm
Location: Peterborough, England
Contact:

Re: Beeb FPGA

Post by fordp » Wed Nov 11, 2015 6:25 pm

JonC wrote:
hoglet wrote: I don't know what's next yet, but I'm sure I'll find something to keep me entertained :D

Dave
Econet/Ethernet solution using an RJ45 port on a wing? :)

This would be great for those who want to build an Econet/L3 Fileserver/Network Bridge etc, but are short on space. :mrgreen:
The wing could also use this econet clock: http://www.stardot.org.uk/forums/viewto ... f=3&t=8000
Econet should be easy too. Just two RS485 drivers needed on the FPGA and the econet chip in HDL.

Cheers.

FordP
FordP (Simon Ellwood)
Time is an illusion. Lunchtime, doubly so!

grannyg
Posts: 44
Joined: Tue Sep 10, 2013 4:06 pm
Contact:

Re: Beeb FPGA

Post by grannyg » Wed Nov 11, 2015 8:21 pm

I've been trying to build the bit file for Beeb Fpga. First I had to copy the contents of AtomBusMon/src into BeebFpga/src/AtomBusmon. Then I get an error about ipcore_dir/WatchEvents.vhd not being found.

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 11, 2015 8:38 pm

grannyg wrote:I've been trying to build the bit file for Beeb Fpga. First I had to copy the contents of AtomBusMon/src into BeebFpga/src/AtomBusmon. Then I get an error about ipcore_dir/WatchEvents.vhd not being found.
This is because I haven't worked out exactly which core gen files needs to be checked in.

You should be able to sort this by regenerating the WatchEvents core (from the .xco file):

Follow the instructions here:
http://www.xilinx.com/support/documenta ... e_core.htm

I should probably just check it the .bit file, but then it's a pain to maintain.

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Wed Nov 11, 2015 8:42 pm

hoglet wrote: I should probably just check it the .bit file, but then it's a pain to maintain.
Here you go:
https://github.com/hoglet67/BeebFpga/bl ... pgaDuo.bit

This needs to be programmed into the Papilio's SPI FLASH - programming it directly into FPGA config RAM won't work. This is because there are various ROM images (e.g. the MOS) appended to the bit file which are then copied from SPI FLASH into SRAM when the system first powers up.

If you are building this yourself, you need to make run the make_master_rom_image.sh script from the roms directory. This takes the .bit file produced by ISE, adds in the firmware image for the ICE-T65, then appends all the ROM images. This currently has lots of dependencies (both tool chain and other FPGA projects, like the ICE T65.

If you (or anyone else) want to build this yourself, I can try to improve this a bit, as the ICE-T65 firmware is quite stable to I could check in a binary.

Dave

User avatar
hoglet
Posts: 9441
Joined: Sat Oct 13, 2012 7:21 pm
Location: Bristol
Contact:

Re: Beeb FPGA

Post by hoglet » Thu Nov 12, 2015 8:39 am

Edited post above....

Post Reply

Return to “8-bit acorn hardware”