I've been looking around for a datasheet for the MEMC1A, but haven't had any luck. I have the MEMC datasheet, and an "ARM Family Data Manual" PDF which mentions the VL86C110, but is missing the pages for its section. Is this around somewhere? I'm curious to see how the master/slave memory behaviour is documented. Is the MEMC chip even aware of this, or is it just a matter of leaving the Vidak, Sndak, Vidw, Sirq, Iorq, Romcs, Phi1, and Phi2 pins disconnected? I can't find anything that tells a MEMC whether it's master or slave. The MEMC datasheet says that one MEMC will occupy the entire memory map; is this what changed with the MEMC1A perhaps?
The best resource I have for this was the A500/R200 service manual, which contains schematics for the A540. It looks like two PALs (IC39, 0286,023) and IC71 (0286,020) generate all the signals; IC39 generates a separate A7 and A22 signal for each MEMC1A (documented in Theo Markettos' email) but also IC71 generates four 'enable' signals, which are used to gate the Clk24m line for each chip. I assume IC71 is just for reset timing (keeping the slave MEMCs from interfering with the boot process, maybe?)... if anyone knows, do tell!
The MEMC1A (VL86C110) datasheet explains what I was looking for. From page 4-8:
~B/W is the byte/word select, so it looks like IC71's job is to generate Sreset*, which holds ~B/W low during reset and ensures that the MEMC1A chips on the RAM cards come up in slave mode.A single MEMC will control up to 4 Mbytes of DRAM. A second MEMC can be built into a system to extend the maximum addressable DRAM to 8 Mbytes. The two MEMCs are configured as a Master and a Slave, where the Slave acts purely as a DRAM driver (all DMA operations, I/O Controller interactions, etc. are handled by the Master).
The ~B/W input is sampled as RES goes low, and its state determines whether the MEMC will operate in Master (~B/W = 1) or Slave (~B/W = 0) mode. In a single MEMC system, VL86C010 holds ~B/W high during reset, so the MEMC is always configured as a Master.
From page 4-13:
Reading more about how the address translator works, it seems that each MEMC has a 128-entry lookup table, where each entry contains a logical page number, then whenever you access memory in the 32MB logical space, the MEMC looks for a lookup table entry containing the logical page number, and maps it to the physical page corresponding to the table entry.In a dual MEMC system, the physical RAM is effectively doubled to 256 physical pages, and the Logical to Physical Address Translators in both the Master and Slave MEMCs must be programmed. When programming the Address Translators, A(7) specifies whether the Master or Slave Address translator is being accessed.
This feels backwards, but I guess it saves memory over having an entry for every logical page; it means 128 13-bit entries (1664 bits) rather than 8192 7-bit entries (57344 bits). This will cause undefined behaviour if more than one table entry contains the same logical page number, because that means you're telling the MEMC to map one logical page to two different locations. If you do this on two different MEMCs you'll end up with a bus conflict.
From Theo's email, it looks like the master responds in the physical memory space when A22=0, and the slave responds when A22=1. The datasheet says that the RAM image is repeated every 128 pages, and later that having a second MEMC effectively doubles the physical RAM to 256 pages, but I don't believe the master MEMC is aware of the existence of a second one, so I'm a bit confused here.