need HELP with 74HC595 timing diagram

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duikkie
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need HELP with 74HC595 timing diagram

Post by duikkie » Tue Dec 10, 2019 2:40 pm

i have two schematics and a timing diagram

first schematic left look at pin11 and 12 and the timing diagram is this wrong ?
on the right they connected pin 12 and 13 is this right ?

now the timing diagram how do you covert ser in parallel ?

pin 10 is vcc = never clear input ( it is a choice)

i do not understand SRclk ( serial clock ) and Rclk ( ??? clk ) looks like srclk=/rclk
so connect pin 11 and pin 12 is difficult to understand

connecting pin 12and 13 can , but why everytime disable output ?

how must i read this

what are the signals on SER pin9 to get QH high ?
what to get QF high and QH high
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74hc595.jpg

cmorley
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Re: need HELP with 74HC595 timing diagram

Post by cmorley » Tue Dec 10, 2019 2:55 pm

Pin 12 clocks the serial register contents into the parallel latch.

Pin 9 is the Q7 serial output used if you are daisy chaining multiple chips for more than 8-bits.

Pin 13 is the output enable (active low).

I would google 74ahct595 say and get the Nexperia and/or Texas Instruments datasheets. The chip operation is the same for LS/AHC/AHCT etc. The datasheet has the pin descriptions and table of functions too.

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1024MAK
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Re: need HELP with 74HC595 timing diagram

Post by 1024MAK » Tue Dec 10, 2019 3:15 pm

26D458B1-CAFF-46D5-B860-699B28E23EBE.jpeg
74HC595 functional diagram
Link to datasheet

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duikkie
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Re: need HELP with 74HC595 timing diagram

Post by duikkie » Tue Dec 10, 2019 3:18 pm

if you look at the picture i have the datasheet for texas intruments.
that do not mean that i understand it #-o

and one of the schematic is wrong ?

cmorley wrote:
Tue Dec 10, 2019 2:55 pm
Pin 12 clocks the serial register contents into the parallel latch.

Pin 9 is the Q7 serial output used if you are daisy chaining multiple chips for more than 8-bits.

Pin 13 is the output enable (active low).

I would google 74ahct595 say and get the Nexperia and/or Texas Instruments datasheets. The chip operation is the same for LS/AHC/AHCT etc. The datasheet has the pin descriptions and table of functions too.

cmorley
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Re: need HELP with 74HC595 timing diagram

Post by cmorley » Tue Dec 10, 2019 3:26 pm

Neither look wrong. They just use the chip slightly differently.

Data in (pin 14) is clocked in with the shift clock (pin 11).

Reset (pin 10) is Vcc on both circuits so inactive.

Data shift out (pin 9) is unused in both circuits.

Latch clock (pin 12) transfers shift register to the latch on the rising edge. So on the left circuit you will see the data move on the outputs because it is clocked with the shift clock. On the right circuit the data will only move over with X1-6 (X1-8? hard to read).

Output enable (pin 13) needs to be low to enable the output. This is connected to ~WOE on the left circuit and the same as the latch like X1-8 on the right circuit. So when X1-8 is low the output is enabled when it goes high the output is disabled but new data is latched.

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