Problems with Verilog bit array.....

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Joined: Sun May 31, 2009 11:52 pm

Problems with Verilog bit array.....

Post by Prime » Mon Mar 20, 2017 9:10 am

Hi all,

Posting this here too as I know some of you also use Verilog and may have some useful input, also since the 6809 bus is similar to the 6502 bus that helps too....

I'm making an addon for an old 6809 based computer, one of the components of this machine (Tandy CoCo) has an IC that is programmed by writing to a series of addresses.
It has 16 programable bits that are programmed by writing to a pair of addresses, for example the first bit is programmed by writing to FFC0 (clear) and FFC1 to set.
Since this chip (74LS783 SAM) has no connection to the data bus of the machine I have no way of reading the values back, so my design has an XC95144XL CPLD attached to the machine's bus.

I have defined a 16 bit word to capture the bits as written, it can be seen from above that once a suitable address range is decoded I should be able to use bits 4:1 of the address bus as a 'register select' and address bit 0 effectivly becomes the data bit.

Once stored I need to be able to read back the data bits as two bytes.

The relevent bits of my code are posted below

Code: Select all

module Main(
    // 6809 side
    input [15:0] Addr,        // Dragon address bus
    inout [7:0] Data,        // Daragon data bus
    input E,                // E clock
    input Q,                // Q clock
    input RW,                // Read/Write
    input Reset,            // System reset

    reg    [15:0]    SAMBits;        // 1 bit x 16 bit array.....
    // Generate OE and WE signals, only do this if Reset is high !
    assign RD            = E & RW & Reset;
    assign WR            = E & ~RW & Reset;

    assign SAMBitsAddr    = ((Addr>=16'hFFC0) && (Addr<=16'hFFDF));
    assign SAMBitsWR    = SAMBitsAddr & WR;
    always @(posedge SAMBitsAddr or negedge Reset)
      if (!Reset)
        case (Addr[5:1])
            4'b0000        : SAMBits[0]    <= Addr[0];
            4'b0001        : SAMBits[1]    <= Addr[0];
            4'b0010        : SAMBits[2]    <= Addr[0];
            4'b0011        : SAMBits[3]    <= Addr[0];
            4'b0100        : SAMBits[4]    <= Addr[0];
            4'b0101        : SAMBits[5]    <= Addr[0];
            4'b0110        : SAMBits[6]    <= Addr[0];
            4'b0111        : SAMBits[7]    <= Addr[0];
            4'b1000        : SAMBits[8]    <= Addr[0];
            4'b1001        : SAMBits[9]    <= Addr[0];
            4'b1010        : SAMBits[10]    <= Addr[0];
            4'b1011        : SAMBits[11]    <= Addr[0];
            4'b1100        : SAMBits[12]    <= Addr[0];
            4'b1101        : SAMBits[13]    <= Addr[0];
            4'b1110        : SAMBits[14]    <= Addr[0];
            4'b1111        : SAMBits[15]    <= Addr[0];
        SAMBits[15:0] <= 0;
    assign SAMBitsH        = (Addr==16'hFF58);
    assign SAMBitsL        = (Addr==16'hFF59);
    assign SAMBitsRD    = (SAMBitsL | SAMBitsH) & RD;
    wire [7:0]    SAMData;
    assign SAMData        = SAMBitsL ? { SAMBits[7], SAMBits[6], SAMBits[5], SAMBits[4], SAMBits[3], SAMBits[2], SAMBits[1], SAMBits[0]} :
                                     { SAMBits[15], SAMBits[14], SAMBits[13], SAMBits[12], SAMBits[11], SAMBits[10], SAMBits[9], SAMBits[8]};

    // When the Dragon reads give it the AVR data / status
    // Note both reading the AVR data reg & the PIA override give the AVRToDragon reg.
    wire [7:0]     DragonDataOut;
    assign     DragonDataOut[7:0]        = SAMBitsRD ? SAMData :
                                      AVRStatus ? {5'b0,AVRW_DragonR,DragonW_AVRR,AVRBusy} :
                                      RamCTRLRD    ? {MapMode,NMIEn,RAMVec,ROMA14, RomWE, FIRQEn, RamWP, RamEnable} :
    assign     Data                    = (DragonIORD | AVRStatusRD | RamCTRLRD | SAMBitsRD | PIACS) ? DragonDataOut : 8'bz;
Note this module also handles other interfacing like enabling disabling roms and data exchange with an AVR microcontroller however that part of the design is working correctly so I have trimmed if from the above code for clarity.

The above code does compile and fit into the chip however when looking at the output equations it all seems to be implemented as FTCPE, which doesn't seem to make sense, as I'm not asking it to toggle

This is the code generated for Sambits[0] for example :

Code: Select all

FTCPE_SAMBits0: FTCPE port map (SAMBits(0),SAMBits_T(0),SAMBits_C(0),SAMBits_CLR(0),SAMBits_PRE(0));
SAMBits_T(0) <= ((Reset AND SAMBits(0))
    OR (NOT Addr(4) AND NOT Addr(2) AND NOT Addr(3) AND NOT Addr(1) AND
    NOT Addr(5) AND SAMBits(0)));
SAMBits_C(0) <= (Addr(9) AND Addr(8) AND Addr(15) AND Addr(14) AND
    Addr(13) AND Addr(12) AND Addr(11) AND Addr(10) AND Addr(6) AND
    Addr(7) AND NOT Addr(5));
SAMBits_CLR(0) <= (NOT Addr(4) AND NOT Addr(2) AND NOT Addr(3) AND NOT Addr(1) AND
    NOT Addr(0) AND NOT Addr(5) AND NOT Reset);
SAMBits_PRE(0) <= (NOT Addr(4) AND NOT Addr(2) AND NOT Addr(3) AND NOT Addr(1) AND
    Addr(0) AND NOT Addr(5) AND NOT Reset);
Anyone have any idea how I can do what I want? Or why the above is not working?



Posts: 797
Joined: Sun Aug 12, 2012 8:47 pm

Re: Problems with Verilog bit array.....

Post by dp11 » Mon Mar 20, 2017 12:15 pm

Just to be clear does the code actually not work in practice ? The compiler has made a logic optimisation from your code to reduce the number of Pterms.

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Posts: 788
Joined: Tue Jul 06, 2010 9:33 pm

Re: Problems with Verilog bit array.....

Post by flynnjs » Sat Mar 25, 2017 7:59 pm

As a first stab in the dark, I suspect it's the "posedge SAMBitsAddr".

You've basically got no data setup time as you're decoding the address
to create a clock and trying to capture Addr[0] all in one go.

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