Search found 1518 matches

by KenLowe
Mon Nov 30, 2020 6:34 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

The STA (ZP), Y takes 6 bus cycles: # address R/W description --- ----------- --- ------------------------------------------ 1 PC R fetch opcode, increment PC 2 PC R fetch pointer address, increment PC 3 pointer R fetch effective address low 4 pointer+1 R fetch effective address high,trafs add Y to...
by KenLowe
Mon Nov 30, 2020 6:13 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Thanks for that explanation. That's very interesting. Do you have a data sheet for the CDP6818E? I've just realised I was quoting the wrong part in my previous post. The two tests were with the CDP6818E and the CDP6818AE. I think the E is just the packaging type (Plastic). The CDP6818A(E) is the new...
by KenLowe
Mon Nov 30, 2020 3:38 pm
Forum: 8-bit acorn hardware
Topic: Clearing EPROMS/EEPROMS
Replies: 55
Views: 1721

Re: Clearing EPROMS/EEPROMS

BeebMaster wrote:
Mon Nov 30, 2020 10:28 am
I did actually ruin a whole tube of 62256 RAMs once by laying them all out and systemically removing the wrong pin!!!
Ouch!
by KenLowe
Mon Nov 30, 2020 12:58 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Might be worth noting that poking in Basic with the ? operator is an indexed operation (I think...) and so the sequence of accesses might not be quite what you expect. Might be worth trying a store absolute in assembly to see if there's any difference. I have been testing on my computer with the V2...
by KenLowe
Sun Nov 29, 2020 10:37 pm
Forum: 8-bit acorn hardware
Topic: Choosing a slice of Pi
Replies: 20
Views: 369

Re: Choosing a slice of Pi

Bobbi wrote:
Sun Nov 29, 2020 10:26 pm
Yes true. But cheaper to buy the $7 one and solder the header for another $2 :) [I am cheap, I admit it!]
If you're happy to solder, then yes.
by KenLowe
Sun Nov 29, 2020 10:24 pm
Forum: 8-bit acorn hardware
Topic: Choosing a slice of Pi
Replies: 20
Views: 369

Re: Choosing a slice of Pi

You can purchase the wireless version with the header pre soldered - It's the Pi Zero WH model.
by KenLowe
Sun Nov 29, 2020 3:08 pm
Forum: 8-bit acorn hardware
Topic: Choosing a slice of Pi
Replies: 20
Views: 369

Re: Choosing a slice of Pi

Have a look at KenLowe's Tube Level Shifter. Very neat and will fit in the Connector Well beside another RPi on the 1MHz Bus port. Yip, have a look here for my level shifter. It includes the facility to solder in a 3 pin debug header. It doesn't come pre soldered by default, but I can add if reques...
by KenLowe
Sun Nov 29, 2020 11:41 am
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

I have slightly lost track of what previous experiments you have done: - did you get the DS12885 working with your through-hole board with the original PALs? I've not tried this in a while. I couldn't get to work the last time I tried it, but that was before I discovered the issue with battery. How...
by KenLowe
Sun Nov 29, 2020 12:31 am
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

I tend to believe the value &D1 is genuinely what is held at address &20. The value I read stays the same, regardless of what I try to write. If I switch to address &21, I consistently read the value &71, and if I switch back to address &20 again I get the value &D1 again That suggests it's the RTC...
by KenLowe
Sat Nov 28, 2020 11:07 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Here's the scope results. Yellow: Phi2 Cyan: RTC_AS Magenta: RTC_DS Blue: RnW The first trace shows (left to right): Write &55 to address &20 (first AS and DS pulse) Read data from address &20 (second AS and DS pulse) Write &AA to address &20 (third AS and DS pulse) Read data from address &20 (forth...
by KenLowe
Sat Nov 28, 2020 10:37 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

With the trigger pulse width set to 100ns, slowly reduce the trigger level from 1V down towards 0V. At some point it will start triggering on noise. Note the trigger level where that occurs. Do this for each of RTC_AS and RTC_DS. If it's less than 0.5V then you are fine. If it's more like 0.8V then...
by KenLowe
Sat Nov 28, 2020 10:11 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

You would be better switching to the scope and using a glitch (or pulse width) triggering mode. Start with the trigger threshold to ~1.0V, and look high going AS or DS pulses that are < 100ns. There should be none. Right, that's me learned something new about my scope. I can confirm that I'm not ge...
by KenLowe
Sat Nov 28, 2020 9:31 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

And here's one of the sections where it's glitchy. Note that Phi2, AS & DS are all temporary outputs from the CPLD. It would be interesting to know if the CPLD is genuinely spitting out those signals, or if the logic analyser is wrongly picking these up: RTC-Capture11.PNG And for reference, here's t...
by KenLowe
Sat Nov 28, 2020 9:22 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

It may just be the logic analyser that's doing funny things. Everything to the right of the trace, where it's shaded is fine. The bit to the left is where I'm getting both AS and DS pulsing at the same time. That just shouldn't be happening. I'm also not sure why I'm getting sections of blank data. ...
by KenLowe
Sat Nov 28, 2020 8:43 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

What's the power supply voltage (VCC), measured close to the RTC chip? 4.97v between pins 12 (Gnd) and 24 (Vcc), and 3.77v between pins 12 (Gnd) and 20 (VBat). My only other thought was whether permanently grounding CS might be an issue. Is this something that worked on the dev board? It's always b...
by KenLowe
Sat Nov 28, 2020 8:35 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

The datasheet states that during a write operation, 'the trailing edge of DS causes the device to latch the written data', and if I'm reading the data sheet correctly I need a minimum 10ns between RTC_DS falling and RnW rising (tRWH) in order to correctly latch in the data? If the 6502 RnW signal t...
by KenLowe
Sat Nov 28, 2020 7:42 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Looking at timing diagram in the datasheet, I'm pretty sure the falling edge of RTC_DS needs to happen before the rising edge of R/nW, but that's not what's happening. Am I reading the timing diagram right? Any thoughts on how best to correct this? The RnW signal on a 6502 will always lag the falli...
by KenLowe
Sat Nov 28, 2020 4:57 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

I think that's expected. The data sheet says: An address strobe must immediately precede each write or read access. (i.e. it doesn't suggest that multiple "data strobe only" cycles are allowed, nor do the timing diagrams show that). Without going down another rabbit hole here, I have noticed that o...
by KenLowe
Sat Nov 28, 2020 4:08 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

That suggests it's the RTC write that is failing. It does indeed. Another odd thing. The results vary depending on whether I have pull up or pull down on the data bus. The data bus is currently terminated with 4k7 resistors. Here's what happens: With pull up: Test 1 Strobe in address &20 Strobe out...
by KenLowe
Sat Nov 28, 2020 3:31 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Here's a trace with a single write of &AA to address &20, followed by multiple reads from address &20. I tend to believe the value &D1 is genuinely what is held at address &20. The value I read stays the same, regardless of what I try to write. If I switch to address &21, I consistently read the val...
by KenLowe
Sat Nov 28, 2020 3:24 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Looking at timing diagram in the datasheet, I'm pretty sure the falling edge of RTC_DS needs to happen before the rising edge of R/nW, but that's not what's happening. Am I reading the timing diagram right? Any thoughts on how best to correct this? The RnW signal on a 6502 will always lag the falli...
by KenLowe
Sat Nov 28, 2020 2:15 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

This time, I've tied RTC_DS to Phi2: wire FE3x = (bbc_ADDRESS[15:4] == 12'hFE3); assign RTC_AS = FE3x && (bbc_ADDRESS[3:2] == 2'b10) && !RnW && Phi2; // &FE38..B -> Address Strobe assign RTC_DS = FE3x && (bbc_ADDRESS[3:2] == 2'b11) && Phi2; // &FE3C..F -> Data Strobe Not exactly what I expected base...
by KenLowe
Sat Nov 28, 2020 1:49 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

That's much better. The FX2 board can capture between 1 and 8 signals at upto 24MHz. However, if you capture between 9 and 16 signals, the max capture rate drops to 12MHz. Dave Ah. Ok, I understand. Because I'm capturing 12 signals, I'm using the 16 bit mode (and therefore limited to 12MHz). Right,...
by KenLowe
Sat Nov 28, 2020 1:30 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Right. Not sure what you mean by the 16 bit wide mode, but here a much more sensible capture. I'll now try writing some data as well through the data strobe:
RTC-Capture2.PNG
More sensible capture...
by KenLowe
Sat Nov 28, 2020 1:11 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Duh #-o

If I run it at 4MHz is that fast enough?
by KenLowe
Sat Nov 28, 2020 1:02 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Got the logic analyser hooked up today. Firstly, very simple code: .start LDA #&55 STA &FE38 LDA #&AA STA &FE38 JMP start In the CPLD, RTC_AS and RTC_DS are defined as follows: wire FE3x = (bbc_ADDRESS[15:4] == 12'hFE3); assign RTC_AS = FE3x && (bbc_ADDRESS[3:2] == 2'b10) && !RnW && Phi2; // &FE38.....
by KenLowe
Thu Nov 26, 2020 4:52 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

Thanks for all the advice, guy. It's very much appreciated. I think I've been convinced on the button cell option - particularly once I started to think a bit more about the Zener barrier option. My initial thoughts were to go with a 3v3 barrier, but thinking about it a bit more, I realise that does...
by KenLowe
Wed Nov 25, 2020 1:59 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

have you got any decoupling on vbat and vdd ? I do have on Vdd, but not on VBat. However, I do currently have a big lump of battery on VBat! I'm sure I'm just stating what you already know here.... The DS12885/7 are designed use a simple non-rechargable 3V lithium coin-cell, like a CR2032, and the ...
by KenLowe
Wed Nov 25, 2020 12:17 pm
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

The series diode didn't work. With nothing connected to the VBat input, I'm measuring about 4.5v on the pin and the RTC does not communicate. If I then take this input and tie it down to Gnd it works fine. Adding the diode prevents the internal voltage on VBat from being pulled down to a low enough...
by KenLowe
Wed Nov 25, 2020 9:33 am
Forum: 8-bit acorn hardware
Topic: Help - Implementing Shadow RAM in CPLD
Replies: 138
Views: 3540

Re: Help - Implementing Shadow RAM in CPLD

You could try a higher value resistor e.g. lower the charging current I went for 150R, based on the discussion in this thread: https://stardot.org.uk/forums/viewtopic.php?f=3&t=13590&p=269287#p265614 and strap a 3V9 Zener across the battery - Although zeners aren't that accurate so maybe a 1N4001 (...

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