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Testing at ABUG today the RAM with buffers on works flawlessly so far. I will post it to steve3000 next week to see if it is fixed in his machine too. If so I will tidy up the PCB layout and release the Gerbers

spider RAM doesn't work I think the long wires are just too poor for crosstalk/signal integrity. I will do a new PCB with the buffers on board.

Steve sent the boards back so I soldered the buffers on this morning (which arrived from RS yesterday). Flipping things are twice the price they were last year - but amusingly buying 150 is cheaper than buying 75 :lol: I'll bring it to ABUG at the weekend then post it to steve3000 again for further ...

Me too... spare pi zero V1.3 not Wifi version

I assume the flying lead means an ordinary switch or button would also be an option for switching configuration? I use CTRL+BREAK quite a lot when using the Beeb, and I'm not sure I want it doing an OS switch each time :) There is a timer in firmware on the switch input currently set to 1.5s which ...

Testing by Steve has shown it doesn't work without buffers. I am not surprised because the A5000 has a discrete MEMC just like the A3000 (which didn't work either). So solder the buffers on next for a retest on the spaces I put on the the board for this very eventuality! I had hoped the A3000 proble...

Steve has done a bunch of testing and it doesn't work in an A4000 reliably. I imagine it is exactly the same problem as the A3000 but I was hoping the ARM250 SoC would have had better signal integrity :( So buffer version ready to test at ABUG. If it works I will redo the PCBs and work out how to fi...

The NAUG/AUG is talking about the 1MHz bus.

The 6845 chip select signal ~CRTC comes from IC26. The gate (output enable) for IC26 comes from IC29 an or gate where high bits address match is ORed with phi1.

So single access only for the CRTC.

Do you mean could E act as enable for a latch rather than a clock for a flip flip (register)? I doubt it or the internals of the 6845 would be subjected to all the spurious data bus values while the data is being set up. Note the datasheet requires the data to be setup before the end of E high not a...

No because the bus is controlled by E (enable) which is 1MhzE. The character generation is done from CLK (clock).

Yellow = 2MHzE
Blue = 1MHzE

even case: odd case: Both cases the clock is 75% duty synchronous to the 1MHzE.

There are two cases for the clock crossing. Only one is shown in the NAUG (and App note 3). The other one is the low phase of the 2MHzE is 250ns and high phase is 750ns (75% duty cycle). The falling edge of 1MHzE and 2MHzE always coincide. Writes from CPU -> device latch at this falling edge. The CP...

Cycle stretching is a poor term. The machine does clock domain crossing. The processor is forced onto the 1MHz clock which remains constant and synchronous. So it is always deterministic - a feature I used for cycle counting on the mode 0 Bad Apple demo. I inserted (reordered) 2 or 3 cycle instructi...

I had similar on a machine. IIRC it was the RSTA circuit - one end of the C or R was never soldered from the factory. So it would sometimes boot but always be OK on a BREAK too.

Your 2.5v on RSTA might have been a real measurement. Check for dry/cracked joints on the R & C Kazzie mentioned.

Potentially... if it works in the system.

The timings for key parameters are faster at typically 60% of the 80ns Toshiba TC514800. So as long as the RAM is compatible then there should be decent headroom for overclocking...

Kazzie wrote: ↑

Wed Sep 11, 2019 5:01 pm

Looks like you've been promoted to Head of MI6!

I can neither confirm or deny.

4mil/4mil and 4 layer board with 3 signal and 1 ground & power.

Yes I have used an STM32F042 which doesn't require a crystal for the USB. Only 32KB of FLASH and 6KB of RAM though.

Super. I will give it a test over the weekend too. Thanks Dave.

What's the programming procedure? Can it be reprogrammed in situ? I'd be very interested in a straightforwardly re-programmable mega rom replacement! USB serial (virtual com port) programming. Yes in situ programming. On the firmware todo list is to allow one of the GPIO outputs to be controlled by...

I'm not fussed about GoSDC/MMC clash. A narrower (harder to assemble) adapter could be made - like my B modules which are only 0.05" wider than the socket. This is really a test of the EPROM emulator. It clears the jumpers and ECONET so that is good enough for me for now. Works though. Control-BREAK...

One board built up for now. No buffers fitted. If they aren't required I will delete them from the PCB when I fix the footprint of the DIN connector.

Two boards complete. The hole is to allow access to LK32 on the motherboard. Hopefully the dimensions are correct.

Master MOS swticher adapter assembled. I will try it this weekend then if successful post one to a forum member for testing
edit: I just noticed the text on the 27C400 emulator is upside down compared to convention of notch on the left... added to the fix list

tricky wrote: ↑

Thu Sep 05, 2019 8:18 pm

I also wonder if SmartSPI is hitting the same issue - I guess so - Duikkie?

I imagine so. I used SmartSPI first when I had trouble with the 128MB card from you - then had similar joy with MMFS.

I've got boobip sideways RAM and EEPROM modules in my B, which is otherwise unexpanded (without even a disc interface) - but I unplugged one of the leads for the ROMSEL test, hopefully disabling them sufficiently. As it happened, the results were the same with or without. I've got BASIC in its orig...

Will it be able to run ZIDEFS so one can mount a 4 partition disk image as per IanS's 8 &16 bit IDE upgrades?

THe QMTech boards are great value. Xilinx and Altera/Intel ones in their lineup. The Aliexpress shop is cheaper than eBay but they are available from both. Took less than a week to arrive too. I bought a couple for prototyping.

File copying was necessary to get the failure because of the extra noise on the A3000 ground. Without the IDE activity the poor signal ground on the A3000 MEMC caused all low signals to be raised on falling edges of MEMC output pins... with the IDE going this tipped it over the TTL threshold causing...

Oh, exciting! I'd happy to volunteer and have an 8mb A5000 so can test with/without the 8mb upgrade fitted. I also have an old 'prototype' 1mb A5000 in the loft, but suspect your design requires 2mb on-board...or does it replace the on-board RAM completely? Splendid thank you. It has 4MB on card an...